mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Fix INIT values

Browse source
This commit is contained in:
Eddie Hung 2019-11-20 11:26:59 -08:00
parent 09ee96e8c2
commit df63d75ff3
1 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

8
techlibs/xilinx/abc9_map.v
View file

@ -96,7 +96,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire $nextQ;
FDRE_1 #(
.INIT(|0),
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
);
@ -205,7 +205,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
endmodule
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
@ -226,10 +226,10 @@ module FDSE (output reg Q, input C, CE, D, S);
wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
endmodule
module FDSE_1 (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
parameter [0:0] INIT = 1'b1;
wire $nextQ;
FDSE_1 #(
.INIT(|0),
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
);