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https://github.com/YosysHQ/yosys
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[ENG-1692] negopt runtime fix + small cleanup
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8 changed files with 123 additions and 12 deletions
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@ -42,6 +42,56 @@ select -assert-count 2 t:$neg
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design -reset
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log -pop
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log -header "Positive case: neg input is sign extension of mux output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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input wire s;
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output wire signed [11:0] y;
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wire signed [7:0] m;
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wire signed [11:0] m_ext;
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assign m = s ? a : b;
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assign m_ext = m;
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assign y = -m_ext;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-count 2 t:$neg
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design -reset
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log -pop
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log -header "Positive case: neg input is zero extension of mux output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, s, y);
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input wire [7:0] a;
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input wire [7:0] b;
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input wire s;
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output wire [11:0] y;
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wire [7:0] m;
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wire [11:0] m_ext;
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assign m = s ? a : b;
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assign m_ext = m;
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assign y = -m_ext;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$mux
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select -assert-count 2 t:$neg
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design -reset
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log -pop
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log -header "Negative case: mux output has extra fanout"
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log -push
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design -reset
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@ -40,6 +40,35 @@ select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: add inputs are sign-extended neg outputs"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [11:0] y;
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wire signed [7:0] na;
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wire signed [7:0] nb;
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wire signed [11:0] na_ext;
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wire signed [11:0] nb_ext;
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assign na = -a;
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assign nb = -b;
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assign na_ext = na;
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assign nb_ext = nb;
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assign y = na_ext + nb_ext;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 2 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Anchor case: neg branches with different widths"
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log -push
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design -reset
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