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Fix minor Yosys issues

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This commit is contained in:
Akash Levy 2025-09-29 12:00:00 -07:00
parent c26f38faeb
commit dee059bee8
2 changed files with 24 additions and 18 deletions
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35
passes/opt/wreduce.cc
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@ -505,34 +505,28 @@ struct WreduceWorker
for (auto w : module->selected_wires()) for (auto w : module->selected_wires())
work_queue_wires.insert(w); work_queue_wires.insert(w);
// Initialize keep bits
for (auto w : module->wires()) {
if (w->get_bool_attribute(ID::keep))
for (auto bit : mi.sigmap(w))
keep_bits.insert(bit);
}
while (!work_queue_cells.empty() && !work_queue_wires.empty()) while (!work_queue_cells.empty() && !work_queue_wires.empty())
{ {
// Initialize keep bits
for (auto w : module->wires()) {
if (w->get_bool_attribute(ID::keep))
for (auto bit : mi.sigmap(w))
keep_bits.insert(bit);
}
// Initialize complete wires // Initialize complete wires
pool<SigSpec> complete_wires; pool<SigSpec> complete_wires;
for (auto w : module->wires()) for (auto w : module->wires())
complete_wires.insert(mi.sigmap(w)); complete_wires.insert(mi.sigmap(w));
// Run wires
for (auto w : work_queue_wires)
run_wire(w, complete_wires);
// Run cells // Run cells
work_queue_bits.clear(); work_queue_bits.clear();
for (auto c : work_queue_cells) for (auto c : work_queue_cells)
run_cell(c); run_cell(c);
// Get next batch of wires to process // Run wires
work_queue_wires.clear(); for (auto w : work_queue_wires)
for (auto bit : work_queue_bits) run_wire(w, complete_wires);
if (bit.wire != NULL && module->selected(bit.wire))
work_queue_wires.insert(bit.wire);
// Get next batch of cells to process // Get next batch of cells to process
work_queue_cells.clear(); work_queue_cells.clear();
@ -541,9 +535,14 @@ struct WreduceWorker
if (module->selected(port.cell)) if (module->selected(port.cell))
work_queue_cells.insert(port.cell); work_queue_cells.insert(port.cell);
// Get next batch of wires to process
work_queue_wires.clear();
for (auto bit : work_queue_bits)
if (bit.wire != NULL && module->selected(bit.wire))
work_queue_wires.insert(bit.wire);
// Reload module // Reload module
if (!work_queue_cells.empty() && !work_queue_wires.empty()) mi.reload_module();
mi.reload_module();
} }
} }
}; };

7
passes/silimate/opt_balance_tree.cc
View file

@ -311,6 +311,9 @@ struct OptBalanceTreePass : public Pass {
log(" -arith\n"); log(" -arith\n");
log(" only convert arithmetic cells.\n"); log(" only convert arithmetic cells.\n");
log("\n"); log("\n");
log(" -logic\n");
log(" only convert logic cells.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override { void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing OPT_BALANCE_TREE pass (cell cascades to trees).\n"); log_header(design, "Executing OPT_BALANCE_TREE pass (cell cascades to trees).\n");
@ -323,6 +326,10 @@ struct OptBalanceTreePass : public Pass {
cell_types = {ID($add), ID($mul)}; cell_types = {ID($add), ID($mul)};
continue; continue;
} }
if (args[argidx] == "-logic") {
cell_types = {ID($and), ID($or), ID($xor)};
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);