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Fixed sign handling in ternary operator

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This commit is contained in:
Clifford Wolf 2013-07-12 01:15:37 +02:00
parent 3cd97a205f
commit ded769c98c
2 changed files with 10 additions and 2 deletions
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4
frontends/ast/genrtlil.cc
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@ -1007,8 +1007,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = std::max(val1.width, val2.width);
is_signed = children[1]->is_signed && children[2]->is_signed;
val1.extend(width);
val2.extend(width);
val1.extend(width, is_signed);
val2.extend(width, is_signed);
return mux2rtlil(this, cond, val1, val2);
}

8
tests/simple/vloghammer.v
View file

@ -57,3 +57,11 @@ module test08(a, b, y);
assign y = a == ($signed(b) >>> 1);
endmodule
module test09(a, b, c, y);
input a;
input signed [1:0] b;
input signed [2:0] c;
output [3:0] y;
assign y = a ? b : c;
endmodule