mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-21 14:45:50 +00:00
Code Activity

Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11

Browse source
This commit is contained in:
Mohamed Gaber 2025-10-26 02:39:43 +03:00
commit dec28f65ae
No known key found for this signature in database
127 changed files with 4674 additions and 7342 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/techmap/clockgate.ys
View file

@ -194,7 +194,7 @@ select -assert-count 1 t:\\pdk_icg
#------------------------------------------------------------------------------
design -load before
clockgate -liberty clockgate.lib
clockgate -liberty c*ckgate.lib
# rising edge ICGs
select -module dffe_00 -assert-count 0 t:\\pos_small

2
tests/techmap/dfflibmap.ys
View file

@ -23,7 +23,7 @@ read_liberty -lib dfflibmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -prepare -liberty dffl*bmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib
design -load orig

16
tests/techmap/techmap_chtype.ys
View file

@ -31,3 +31,19 @@ opt
techmap -map %techmap
select -assert-count 1 t:LCU_8
design -reset
read_verilog <<EOT
module top(input A, input B, output Y);
assign Y = A ^ B;
endmodule
EOT
# We can only test that the option doesn't crash
# See https://github.com/YosysHQ/yosys/issues/5414
# select -assert-count 1 t:$xor
# select -assert-count 0 t:\$xor
chtype -publish_icells
# select -assert-count 0 t:$xor
# select -assert-count 1 t:\$xor