mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-25 16:42:35 +00:00
Code Activity

Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11

Browse source
This commit is contained in:
Mohamed Gaber 2025-10-26 02:39:43 +03:00
commit dec28f65ae
No known key found for this signature in database
127 changed files with 4674 additions and 7342 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/techmap/abc9.cc
View file

@ -38,8 +38,8 @@ struct Abc9Pass : public ScriptPass
Abc9Pass() : ScriptPass("abc9", "use ABC9 for technology mapping") { }
void on_register() override
{
RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f -r; &ps; &if {C} {W} {D} {R} -v; &mfs";
RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f -r; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
RTLIL::constpad["abc9.script.default.fast"] = "+&if {C} {W} {D} {R} -v";
// Based on ABC's &flow
RTLIL::constpad["abc9.script.flow"] = "+&scorr; &sweep;" \

2
passes/techmap/abc9_ops.cc
View file

@ -1605,6 +1605,7 @@ static void replace_zbufs(Design *design)
mod->bufNormalize();
}
design->bufNormalize(false);
}
@ -1624,7 +1625,6 @@ static void restore_zbufs(Design *design)
mod->addBuf(NEW_ID, Const(State::Sz, GetSize(sig_y)), sig_y);
mod->remove(cell);
}
mod->bufNormalize();
}
}

11
passes/techmap/abc_new.cc
View file

@ -141,7 +141,11 @@ struct AbcNewPass : public ScriptPass {
selected_modules = order_modules(active_design,
active_design->selected_whole_modules_warn());
active_design->push_empty_selection();
} else {
}
run("abc9_ops -replace_zbufs");
if (help_mode) {
selected_modules = {nullptr};
run("foreach module in selection");
}
@ -169,13 +173,10 @@ struct AbcNewPass : public ScriptPass {
}
run(stringf(" abc9_ops -write_box %s/input.box", tmpdir));
run(" abc9_ops -replace_zbufs");
run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir));
run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
modname.c_str(), tmpdir.c_str(), tmpdir.c_str()));
run(" abc9_ops -restore_zbufs");
if (!help_mode && mod->has_attribute(ID(abc9_script))) {
if (script_save.empty())
active_design->scratchpad_unset("abc9.script");
@ -196,6 +197,8 @@ struct AbcNewPass : public ScriptPass {
}
}
run("abc9_ops -restore_zbufs");
if (!help_mode) {
active_design->pop_selection();
}

62
passes/techmap/alumacc.cc
View file

@ -40,34 +40,51 @@ struct AlumaccWorker
{
std::vector<RTLIL::Cell*> cells;
RTLIL::SigSpec a, b, c, y;
std::vector<tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
std::vector<tuple<bool, bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
bool is_signed, invert_b;
RTLIL::Cell *alu_cell;
RTLIL::SigSpec cached_lt, cached_gt, cached_eq, cached_ne;
RTLIL::SigSpec cached_lt, cached_slt, cached_gt, cached_sgt, cached_eq, cached_ne;
RTLIL::SigSpec cached_cf, cached_of, cached_sf;
RTLIL::SigSpec get_lt() {
if (GetSize(cached_lt) == 0) {
if (is_signed) {
RTLIL::SigSpec get_lt(bool is_signed) {
if (is_signed) {
if (GetSize(cached_slt) == 0) {
get_of();
get_sf();
cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
cached_slt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
}
else
return cached_slt;
} else {
if (GetSize(cached_lt) == 0) {
cached_lt = get_cf();
}
return cached_lt;
}
return cached_lt;
}
RTLIL::SigSpec get_gt() {
if (GetSize(cached_gt) == 0) {
get_lt();
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
RTLIL::SigSpec get_gt(bool is_signed) {
if (is_signed) {
if (GetSize(cached_sgt) == 0) {
get_lt(is_signed);
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_slt, cached_eq);
cached_sgt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
}
return cached_sgt;
} else {
if (GetSize(cached_gt) == 0) {
get_lt(is_signed);
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
}
return cached_gt;
}
return cached_gt;
}
RTLIL::SigSpec get_eq() {
@ -409,7 +426,7 @@ struct AlumaccWorker
alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
if (node->invert_b && node->c == State::S1) {
n = node;
break;
}
@ -439,7 +456,7 @@ struct AlumaccWorker
}
n->cells.push_back(cell);
n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, Y));
n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, is_signed, Y));
}
for (auto cell : eq_cells)
@ -454,7 +471,7 @@ struct AlumaccWorker
alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
if (node->invert_b && node->c == State::S1) {
n = node;
break;
}
@ -470,7 +487,7 @@ struct AlumaccWorker
if (n != nullptr) {
log(" creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
n->cells.push_back(cell);
n->cmp.push_back(std::make_tuple(false, false, cmp_equal, !cmp_equal, Y));
n->cmp.push_back(std::make_tuple(false, false, cmp_equal, !cmp_equal, false, Y));
}
}
}
@ -525,11 +542,12 @@ struct AlumaccWorker
bool cmp_gt = std::get<1>(it);
bool cmp_eq = std::get<2>(it);
bool cmp_ne = std::get<3>(it);
RTLIL::SigSpec cmp_y = std::get<4>(it);
bool is_signed = std::get<4>(it);
RTLIL::SigSpec cmp_y = std::get<5>(it);
RTLIL::SigSpec sig;
if (cmp_lt) sig.append(n->get_lt());
if (cmp_gt) sig.append(n->get_gt());
if (cmp_lt) sig.append(n->get_lt(is_signed));
if (cmp_gt) sig.append(n->get_gt(is_signed));
if (cmp_eq) sig.append(n->get_eq());
if (cmp_ne) sig.append(n->get_ne());

4
passes/techmap/clockgate.cc
View file

@ -290,9 +290,7 @@ struct ClockgatePass : public Pass {
continue;
}
if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
std::string liberty_file = args[++argidx];
rewrite_filename(liberty_file);
liberty_files.push_back(liberty_file);
append_globbed(liberty_files, args[++argidx]);
continue;
}
if (args[argidx] == "-dont_use" && argidx+1 < args.size()) {

4
passes/techmap/dfflibmap.cc
View file

@ -609,9 +609,7 @@ struct DfflibmapPass : public Pass {
{
std::string arg = args[argidx];
if (arg == "-liberty" && argidx+1 < args.size()) {
std::string liberty_file = args[++argidx];
rewrite_filename(liberty_file);
liberty_files.push_back(liberty_file);
append_globbed(liberty_files, args[++argidx]);
continue;
}
if (arg == "-prepare") {

4
passes/techmap/libcache.cc
View file

@ -96,9 +96,7 @@
quiet = true;
continue;
}
std::string fname = args[argidx];
rewrite_filename(fname);
paths.push_back(fname);
append_globbed(paths, args[argidx]);
break;
}
int modes = enable + disable + purge + list + verbose + quiet;