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https://github.com/YosysHQ/yosys
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signorm: skip const when fixing fanout
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parent
869a7303b0
commit
debc2c3977
1 changed files with 8 additions and 2 deletions
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@ -143,7 +143,8 @@ struct RTLIL::SigNormIndex
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continue;
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continue;
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int i = 0;
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int i = 0;
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for (auto bit : sig)
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for (auto bit : sig)
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fanout[bit].insert(PortBit(cell, port, i++));
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if (bit.is_wire())
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fanout[bit].insert(PortBit(cell, port, i++));
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}
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}
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}
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}
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}
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}
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@ -963,6 +964,8 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
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auto &fanout = module->sig_norm_index->fanout;
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auto &fanout = module->sig_norm_index->fanout;
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int counter = 0;
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int counter = 0;
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for (auto bit : conn_it->second) {
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for (auto bit : conn_it->second) {
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if (!bit.is_wire())
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continue;
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int i = counter++;
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int i = counter++;
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auto found = fanout.find(bit);
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auto found = fanout.find(bit);
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log_assert(found != fanout.end());
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log_assert(found != fanout.end());
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@ -1090,6 +1093,8 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
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auto &fanout = module->sig_norm_index->fanout;
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auto &fanout = module->sig_norm_index->fanout;
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int counter = 0;
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int counter = 0;
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for (auto bit : conn_it->second) {
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for (auto bit : conn_it->second) {
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if (!bit.is_wire())
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continue;
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int i = counter++;
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int i = counter++;
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auto found = fanout.find(bit);
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auto found = fanout.find(bit);
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log_assert(found != fanout.end());
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log_assert(found != fanout.end());
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@ -1111,7 +1116,8 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
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auto &fanout = module->sig_norm_index->fanout;
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auto &fanout = module->sig_norm_index->fanout;
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int i = 0;
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int i = 0;
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for (auto bit : signal)
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for (auto bit : signal)
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fanout[bit].insert(PortBit(this, portname, i++));
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if (bit.is_wire())
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fanout[bit].insert(PortBit(this, portname, i++));
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} else if (GetSize(signal)) {
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} else if (GetSize(signal)) {
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Wire *w = signal.as_wire();
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Wire *w = signal.as_wire();
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log_assert(w->driverCell_ == nullptr);
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log_assert(w->driverCell_ == nullptr);
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