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	timinginfo: Error instead of segfault on const signals.
Reported by @Ravenslofty
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					 1 changed files with 2 additions and 2 deletions
				
			
		|  | @ -88,10 +88,10 @@ struct TimingInfo | ||||||
| 				auto src = cell->getPort(ID::SRC); | 				auto src = cell->getPort(ID::SRC); | ||||||
| 				auto dst = cell->getPort(ID::DST); | 				auto dst = cell->getPort(ID::DST); | ||||||
| 				for (const auto &c : src.chunks()) | 				for (const auto &c : src.chunks()) | ||||||
| 					if (!c.wire->port_input) | 					if (!c.wire || !c.wire->port_input) | ||||||
| 						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); | 						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); | ||||||
| 				for (const auto &c : dst.chunks()) | 				for (const auto &c : dst.chunks()) | ||||||
| 					if (!c.wire->port_output) | 					if (!c.wire || !c.wire->port_output) | ||||||
| 						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); | 						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); | ||||||
| 				int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); | 				int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); | ||||||
| 				int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); | 				int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); | ||||||
|  |  | ||||||
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