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					 5 changed files with 68 additions and 10 deletions
				
			
		
							
								
								
									
										6
									
								
								tests/various/integer_range_bad_syntax.ys
									
										
									
									
									
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										6
									
								
								tests/various/integer_range_bad_syntax.ys
									
										
									
									
									
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logger -expect error "syntax error, unexpected" 1
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read_verilog -sv <<EOT
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module test_integer_range();
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parameter integer [31:0] a = 0;
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endmodule
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EOT
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										6
									
								
								tests/various/integer_real_bad_syntax.ys
									
										
									
									
									
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										6
									
								
								tests/various/integer_real_bad_syntax.ys
									
										
									
									
									
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			@ -0,0 +1,6 @@
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logger -expect error "syntax error, unexpected TOK_REAL" 1
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read_verilog -sv <<EOT
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module test_integer_real();
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parameter integer real a = 0;
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endmodule
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EOT
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										9
									
								
								tests/various/logic_param_simple.ys
									
										
									
									
									
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										9
									
								
								tests/various/logic_param_simple.ys
									
										
									
									
									
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			@ -0,0 +1,9 @@
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read_verilog -sv <<EOT
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module test_logic_param();
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parameter logic                 a = 0;
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parameter logic [31:0]          e = 0;
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parameter logic signed          b = 0;
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parameter logic unsigned        c = 0;
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parameter logic unsigned [31:0] d = 0;
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endmodule
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EOT
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										28
									
								
								tests/various/signed.ys
									
										
									
									
									
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										28
									
								
								tests/various/signed.ys
									
										
									
									
									
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			@ -0,0 +1,28 @@
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# SV LRM A2.2.1
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read_verilog -sv <<EOT
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module test_signed();
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parameter integer signed  a = 0;
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parameter integer unsigned  b = 0;
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endmodule
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EOT
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design -reset
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read_verilog -sv <<EOT
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module test_signed();
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parameter logic signed [7:0] a = 0;
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parameter logic unsigned [7:0] b = 0;
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endmodule
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EOT
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design -reset
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logger -expect error "syntax error, unexpected TOK_INTEGER" 1
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read_verilog -sv <<EOT
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module test_signed();
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parameter signed integer a = 0;
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parameter unsigned integer b = 0;
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endmodule
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EOT
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