mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

Revert "Revert PRs #2203 and #2244."

Browse source 
This reverts commit 9c120b89ac.
This commit is contained in:
Kamil Rakoczy 2020-07-10 09:59:48 +02:00
parent c0bcbe1f62
commit de649b9194
5 changed files with 68 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/various/integer_range_bad_syntax.ys Normal file
View file

@ -0,0 +1,6 @@
logger -expect error "syntax error, unexpected" 1
read_verilog -sv <<EOT
module test_integer_range();
parameter integer [31:0] a = 0;
endmodule
EOT

6
tests/various/integer_real_bad_syntax.ys Normal file
View file

@ -0,0 +1,6 @@
logger -expect error "syntax error, unexpected TOK_REAL" 1
read_verilog -sv <<EOT
module test_integer_real();
parameter integer real a = 0;
endmodule
EOT

9
tests/various/logic_param_simple.ys Normal file
View file

@ -0,0 +1,9 @@
read_verilog -sv <<EOT
module test_logic_param();
parameter logic a = 0;
parameter logic [31:0] e = 0;
parameter logic signed b = 0;
parameter logic unsigned c = 0;
parameter logic unsigned [31:0] d = 0;
endmodule
EOT

28
tests/various/signed.ys Normal file
View file

@ -0,0 +1,28 @@
# SV LRM A2.2.1
read_verilog -sv <<EOT
module test_signed();
parameter integer signed a = 0;
parameter integer unsigned b = 0;
endmodule
EOT
design -reset
read_verilog -sv <<EOT
module test_signed();
parameter logic signed [7:0] a = 0;
parameter logic unsigned [7:0] b = 0;
endmodule
EOT
design -reset
logger -expect error "syntax error, unexpected TOK_INTEGER" 1
read_verilog -sv <<EOT
module test_signed();
parameter signed integer a = 0;
parameter unsigned integer b = 0;
endmodule
EOT