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Reword

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This commit is contained in:
Eddie Hung 2019-07-08 22:56:19 -07:00
parent 7f964859ec
commit de40453553
1 changed files with 2 additions and 2 deletions
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4
techlibs/xilinx/cells_map.v
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@ -202,7 +202,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
end end
else if (A_WIDTH <= 2 ** 3) begin else if (A_WIDTH <= 2 ** 3) begin
// Rather than extend with 1'bx which gets flattened to 1'b0 // Rather than extend with 1'bx which gets flattened to 1'b0
// causing the "don't care" state to get lost, extend with MSB // causing the "don't care" status to get lost, extend with MSB
// so that we can recognise again later when mapping MUXF78 // so that we can recognise again later when mapping MUXF78
wire [8-1:0] Ax = {{(8-A_WIDTH){A[A_WIDTH-1]}}, A}; wire [8-1:0] Ax = {{(8-A_WIDTH){A[A_WIDTH-1]}}, A};
wire T0 = B[0] ? Ax[1] : Ax[0]; wire T0 = B[0] ? Ax[1] : Ax[0];
@ -213,7 +213,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
end end
else if (A_WIDTH <= 2 ** 4) begin else if (A_WIDTH <= 2 ** 4) begin
// Rather than extend with 1'bx which gets flattened to 1'b0 // Rather than extend with 1'bx which gets flattened to 1'b0
// causing the "don't care" state to get lost, extend with MSB // causing the "don't care" status to get lost, extend with MSB
// so that we can recognise again later when mapping MUXF78 // so that we can recognise again later when mapping MUXF78
wire [16-1:0] Ax = {{(16-A_WIDTH){A[A_WIDTH-1]}}, A}; wire [16-1:0] Ax = {{(16-A_WIDTH){A[A_WIDTH-1]}}, A};
wire T0 = B[1] ? B[0] ? Ax[ 3] : Ax[ 2] wire T0 = B[1] ? B[0] ? Ax[ 3] : Ax[ 2]