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Support param. default values in JSON FE and SV BE

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This commit is contained in:
Gus Smith 2022-06-22 10:57:46 -07:00
parent b2408df313
commit de37070c28
2 changed files with 14 additions and 0 deletions
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11
backends/verilog/verilog_backend.cc
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@ -395,6 +395,14 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
}
}
void dump_parameter(std::ostream &f, std::string indent, RTLIL::IdString id_string, RTLIL::Const parameter)
{
f << stringf("%sparameter %s", indent.c_str(), id(id_string).c_str());
f << stringf(" = ");
dump_const(f, parameter);
f << stringf(";\n");
}
void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
{
dump_attributes(f, indent, wire->attributes, '\n', /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name));
@ -2084,6 +2092,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
}
for (auto p : module->parameter_default_values)
dump_parameter(f, indent + " ", p.first, p.second);
for (auto w : module->wires())
dump_wire(f, indent + " ", w);