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Testing TDP synth mapping

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New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
This commit is contained in:
KrystalDelusion 2022-07-05 11:18:43 +12:00
parent 48f4e09202
commit de2f140c09
3 changed files with 49 additions and 0 deletions
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8
tests/arch/gatemate/memory.ys
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@ -6,6 +6,14 @@ cd sync_ram_sdp
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_BRAM_20K
# 512 x 20 bit x 2 -> CC_BRAM_20K TDP RAM
design -reset
read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 20 sync_ram_tdp
synth_gatemate -top sync_ram_tdp -noiopad
select -assert-count 2 t:CC_BUFG
select -assert-count 1 t:CC_BRAM_20K
# 512 x 80 bit -> CC_BRAM_40K SDP RAM
design -reset
read_verilog ../common/blockram.v