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Testing TDP synth mapping

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New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
This commit is contained in:
KrystalDelusion 2022-07-05 11:18:43 +12:00
parent 48f4e09202
commit de2f140c09
3 changed files with 49 additions and 0 deletions
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10
tests/arch/ecp5/memories.ys
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@ -260,3 +260,13 @@ setattr -set logic_block 1 m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
select -assert-min 9 t:LUT4
# ============================== TDP RAM ==============================
# RAM bits <= 18K; Data width <= 18x2; Address width <= 9: -> DP16KD
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp
hierarchy -top sync_ram_tdp
synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp
select -assert-count 1 t:DP16KD
select -assert-none t:LUT4