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Testing TDP synth mapping

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New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
This commit is contained in:
KrystalDelusion 2022-07-05 11:18:43 +12:00
parent 48f4e09202
commit de2f140c09
3 changed files with 49 additions and 0 deletions
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31
tests/arch/common/blockram.v
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@ -45,3 +45,34 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
endmodule // sync_ram_sdp
`default_nettype none
module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
(input wire clk_a, clk_b,
input wire write_enable_a, write_enable_b,
input wire read_enable_a, read_enable_b,
input wire [DATA_WIDTH-1:0] write_data_a, write_data_b,
input wire [ADDRESS_WIDTH-1:0] addr_a, addr_b,
output reg [DATA_WIDTH-1:0] read_data_a, read_data_b);
localparam WORD = (DATA_WIDTH-1);
localparam DEPTH = (2**ADDRESS_WIDTH-1);
reg [WORD:0] mem [0:DEPTH];
always @(posedge clk_a) begin
if (write_enable_a)
mem[addr_a] <= write_data_a;
else
read_data_a <= mem[addr_a];
end
always @(posedge clk_b) begin
if (write_enable_b)
mem[addr_b] <= write_data_b;
else
read_data_b <= mem[addr_b];
end
endmodule // sync_ram_tdp