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Merge pull request #736 from whitequark/select_assert_list

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select: print selection if a -assert-* flag causes an error
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Clifford Wolf 2018-12-16 16:45:49 +01:00 • committed by GitHub
commit ddff75b60a
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2 changed files with 51 additions and 9 deletions
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backends/verilog/verilog_backend.cc
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@ -1421,7 +1421,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
"can't always be mapped directly to Verilog always blocks. Unintended\n"
"changes in simulation behavior are possible! Use \"proc\" to convert\n"
"processes to logic networks and registers.", log_id(module));
"processes to logic networks and registers.\n", log_id(module));
f << stringf("\n");
for (auto it = module->processes.begin(); it != module->processes.end(); ++it)