mirror of
https://github.com/YosysHQ/yosys
synced 2026-01-06 02:52:44 +00:00
Add -legalize option to read_rtlil
This commit is contained in:
parent
914e14946d
commit
ddd6a16ee0
3 changed files with 131 additions and 20 deletions
|
|
@ -3039,6 +3039,13 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
|
|||
}
|
||||
}
|
||||
|
||||
void RTLIL::Module::remove(RTLIL::Memory *memory)
|
||||
{
|
||||
log_assert(memories.count(memory->name) != 0);
|
||||
memories.erase(memory->name);
|
||||
delete memory;
|
||||
}
|
||||
|
||||
void RTLIL::Module::remove(RTLIL::Process *process)
|
||||
{
|
||||
log_assert(processes.count(process->name) != 0);
|
||||
|
|
|
|||
|
|
@ -2139,6 +2139,8 @@ public:
|
|||
}
|
||||
|
||||
RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
|
||||
int wires_size() const { return wires_.size(); }
|
||||
RTLIL::Wire* wire_at(int index) const { return wires_.element(index)->second; }
|
||||
RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
|
||||
|
||||
void add(RTLIL::Binding *binding);
|
||||
|
|
@ -2146,6 +2148,7 @@ public:
|
|||
// Removing wires is expensive. If you have to remove wires, remove them all at once.
|
||||
void remove(const pool<RTLIL::Wire*> &wires);
|
||||
void remove(RTLIL::Cell *cell);
|
||||
void remove(RTLIL::Memory *memory);
|
||||
void remove(RTLIL::Process *process);
|
||||
|
||||
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue