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timinginfo: arrival/required times with clocks

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This commit is contained in:
Eddie Hung 2020-02-18 18:00:07 -08:00
parent b96866c456
commit ddbe81df78
4 changed files with 63 additions and 66 deletions
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44
kernel/timinginfo.h
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@ -36,6 +36,7 @@ struct TimingInfo
explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
bool operator!=(const NameBit& nb) const { return !operator==(nb); }
bool operator<(const NameBit& nb) const { return nb.name < name && nb.offset < offset; }
unsigned int hash() const { return mkhash_add(name.hash(), offset); }
};
struct BitBit
@ -49,9 +50,8 @@ struct TimingInfo
struct ModuleTiming
{
RTLIL::IdString type;
dict<BitBit, int> comb;
dict<NameBit, int> arrival, required;
dict<NameBit, std::pair<int,NameBit>> arrival, required;
};
dict<RTLIL::IdString, ModuleTiming> data;
@ -117,26 +117,26 @@ struct TimingInfo
}
}
else if (cell->type == ID($specify3)) {
auto src = cell->getPort(ID::SRC);
auto src = cell->getPort(ID::SRC).as_bit();
auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
if (!src.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);
if (max < 0)
log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
if (max <= 0) {
log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
continue;
if (max < 0) {
log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported; clamping to zero .\n", log_id(module), log_id(cell));
max = 0;
}
for (const auto &d : dst) {
auto &v = t.arrival[NameBit(d)];
v = std::max(v, max);
if (v.first < max) {
v.first = max;
v.second = NameBit(src);
}
}
}
else if (cell->type == ID($specrule)) {
@ -144,23 +144,23 @@ struct TimingInfo
if (type != "$setup" && type != "$setuphold")
continue;
auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID::DST);
auto dst = cell->getPort(ID::DST).as_bit();
for (const auto &c : src.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
if (!dst.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
if (max < 0)
log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
if (max <= 0) {
log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
continue;
if (max < 0) {
log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported; clamping to zero.\n", log_id(module), log_id(cell));
max = 0;
}
for (const auto &s : src) {
auto &v = t.required[NameBit(s)];
v = std::max(v, max);
if (v.first < max) {
v.first = max;
v.second = NameBit(dst);
}
}
}
}