Merge branch 'master' into eddie/script_from_wire

CHANGELOG

@@ -9,6 +9,17 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "script -select"
 
 
+Yosys 0.9 .. Yosys 0.9-dev
+--------------------------
+
+ * Various
+    - Added "write_xaiger" backend
+    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+    - Added "synth_xilinx -abc9" (experimental)
+    - Added "synth_ice40 -abc9" (experimental)
+    - Added "synth -abc9" (experimental)
+
+
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------
 
@@ -32,11 +43,6 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "synth_xilinx -nocarry"
     - Added "synth_xilinx -nowidelut"
     - Added "synth_ecp5 -nowidelut"
-    - Added "write_xaiger" backend
-    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
-    - Added "synth_xilinx -abc9" (experimental)
-    - Added "synth_ice40 -abc9" (experimental)
-    - Added "synth -abc9" (experimental)
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 

passes/techmap/Makefile.inc

@@ -10,6 +10,7 @@ OBJS += passes/techmap/abc.o
 OBJS += passes/techmap/abc9.o
 ifneq ($(ABCEXTERNAL),)
 passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
+passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
 endif
 endif
 

techlibs/ecp5/Makefile.inc

@@ -13,6 +13,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk

techlibs/xilinx/Makefile.inc

@@ -30,8 +30,10 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))