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Merge pull request #5336 from rocallahan/remove-log-cstr

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Remove `.c_str()` calls from `log()`/`log_error()`
This commit is contained in:
Jannis Harder 2025-09-12 14:09:48 +02:00 • committed by GitHub
commit dd9627ed05
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GPG key ID: B5690EEEBB952194
140 changed files with 623 additions and 623 deletions
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2
passes/cmds/abstract.cc
View file

@ -67,7 +67,7 @@ struct Slice {
int wire_offset(RTLIL::Wire *wire, int index) const {
int rtl_offset = indices == RtlilSlice ? index : wire->from_hdl_index(index);
if (rtl_offset < 0 || rtl_offset >= wire->width) {
log_error("Slice %s is out of bounds for wire %s in module %s", to_string().c_str(), log_id(wire), log_id(wire->module));
log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), log_id(wire), log_id(wire->module));
}
return rtl_offset;
}

14
passes/cmds/add.cc
View file

@ -38,22 +38,22 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_assert(is_formal_celltype(celltype));
if (wire == nullptr) {
log_error("Could not find wire with name \"%s\".\n", name.c_str());
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
formal_cell->setPort(ID::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name);
}
else {
RTLIL::Wire *enable_wire = module->wire(escaped_enable_name);
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
log_error("Could not find enable wire with name \"%s\".\n", enable_name);
formal_cell->setPort(ID::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name);
}
}
}
@ -79,7 +79,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
if (wire == nullptr)
log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
log("Module %s already has such an object.\n", module->name.c_str());
log("Module %s already has such an object.\n", module->name);
}
else
{
@ -91,7 +91,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
module->fixup_ports();
}
log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
log("Added wire %s to module %s.\n", name, module->name);
}
if (!flag_global)
@ -110,7 +110,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
continue;
cell->setPort(name, wire);
log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str());
log("Added connection %s to cell %s.%s (%s).\n", name, module->name, cell->name, cell->type);
}
}

2
passes/cmds/cover.cc
View file

@ -146,7 +146,7 @@ struct CoverPass : public Pass {
for (auto f : out_files)
fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());
if (do_log)
log("%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());
log("%-60s %10d %s\n", it.second.first, it.second.second, it.first);
}
#else
for (auto f : out_files)

2
passes/cmds/edgetypes.cc
View file

@ -105,7 +105,7 @@ struct EdgetypePass : public Pass {
edge_cache.sort();
for (auto &str : edge_cache)
log("%s\n", str.c_str());
log("%s\n", str);
}
} EdgetypePass;

2
passes/cmds/exec.cc
View file

@ -172,7 +172,7 @@ struct ExecPass : public Pass {
std::string line = linebuf.substr(0, pos);
linebuf.erase(0, pos + 1);
if (!flag_quiet)
log("%s\n", line.c_str());
log("%s\n", line);
if (flag_expect_stdout)
for(auto &x : expect_stdout)

2
passes/cmds/glift.cc
View file

@ -343,7 +343,7 @@ private:
//with taint signals and connect the new ports to the corresponding taint signals.
RTLIL::Module *cell_module_def = module->design->module(cell->type);
dict<RTLIL::IdString, RTLIL::SigSpec> orig_ports = cell->connections();
log("Adding cell %s\n", cell_module_def->name.c_str());
log("Adding cell %s\n", cell_module_def->name);
for (auto &it : orig_ports) {
RTLIL::SigSpec port = it.second;
RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port);

8
passes/cmds/internal_stats.cc
View file

@ -100,15 +100,15 @@ struct InternalStatsPass : public Pass {
if (json_mode) {
log("{\n");
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str());
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump());
std::stringstream invocation;
std::copy(args.begin(), args.end(), std::ostream_iterator<std::string>(invocation, " "));
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str());
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump());
if (auto mem = current_mem_bytes()) {
log(" \"memory_now\": %s,\n", std::to_string(*mem).c_str());
log(" \"memory_now\": %s,\n", std::to_string(*mem));
}
auto ast_bytes = AST::astnode_count() * (unsigned long long) sizeof(AST::AstNode);
log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes).c_str());
log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes));
}
// stats go here

4
passes/cmds/linecoverage.cc
View file

@ -85,7 +85,7 @@ struct CoveragePass : public Pass {
if (!ofile.empty()) {
fout.open(ofile, std::ios::out | std::ios::trunc);
if (!fout.is_open())
log_error("Could not open file \"%s\" with write access.\n", ofile.c_str());
log_error("Could not open file \"%s\" with write access.\n", ofile);
}
std::map<std::string, std::set<int>> uncovered_lines;
@ -128,7 +128,7 @@ struct CoveragePass : public Pass {
for (const auto& file_entry : all_lines) {
int lines_found = file_entry.second.size();
int lines_hit = file_entry.second.size() - (uncovered_lines.count(file_entry.first) ? uncovered_lines[file_entry.first].size() : 0);
log("File %s: %d/%d lines covered\n", file_entry.first.c_str(), lines_hit, lines_found);
log("File %s: %d/%d lines covered\n", file_entry.first, lines_hit, lines_found);
if(!ofile.empty()) {
fout << "SF:" << file_entry.first << "\n";

2
passes/cmds/logcmd.cc
View file

@ -106,7 +106,7 @@ struct LogPass : public Pass {
if (to_stdout) fprintf(stdout, "%s%s", text.c_str(), line_end);
if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end);
if (to_log) {
if (!header) log("%s%s", text.c_str(), line_end);
if (!header) log("%s%s", text, line_end);
else log_header(design, "%s%s", text.c_str(), line_end);
}
}

8
passes/cmds/logger.cc
View file

@ -108,7 +108,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to warn list.\n", pattern.c_str());
log("Added regex '%s' for warnings to warn list.\n", pattern);
log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -120,7 +120,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to nowarn list.\n", pattern.c_str());
log("Added regex '%s' for warnings to nowarn list.\n", pattern);
log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -132,7 +132,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to werror list.\n", pattern.c_str());
log("Added regex '%s' for warnings to werror list.\n", pattern);
log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -152,7 +152,7 @@ struct LoggerPass : public Pass {
}
if (args[argidx] == "-experimental" && argidx+1 < args.size()) {
std::string value = args[++argidx];
log("Added '%s' experimental ignore list.\n", value.c_str());
log("Added '%s' experimental ignore list.\n", value);
log_experimentals_ignored.insert(value);
continue;
}

6
passes/cmds/plugin.cc
View file

@ -187,11 +187,11 @@ struct PluginPass : public Pass {
log("Loaded plugins:\n");
for (auto &it : loaded_plugins)
log(" %s\n", it.first.c_str());
log(" %s\n", it.first);
#ifdef WITH_PYTHON
for (auto &it : loaded_python_plugins)
log(" %s\n", it.first.c_str());
log(" %s\n", it.first);
#endif
if (!loaded_plugin_aliases.empty()) {
@ -200,7 +200,7 @@ struct PluginPass : public Pass {
for (auto &it : loaded_plugin_aliases)
max_alias_len = max(max_alias_len, GetSize(it.first));
for (auto &it : loaded_plugin_aliases)
log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str());
log("Alias: %-*s %s\n", max_alias_len, it.first, it.second);
}
}
}

2
passes/cmds/portarcs.cc
View file

@ -278,7 +278,7 @@ struct PortarcsPass : Pass {
log("\n");
for (auto bit : outputs) {
log(" %10s ", bit_str(bit).c_str());
log(" %10s ", bit_str(bit));
int *p = annotations.at(canonical_bit(bit));
for (auto i = 0; i < inputs.size(); i++)
log("\033[48;5;%dm ", 232 + ((std::max(p[i], 0) * 24) - 1) / max_delay);

2
passes/cmds/portlist.cc
View file

@ -75,7 +75,7 @@ struct PortlistPass : public Pass {
}
log("module %s%s\n", log_id(module), m_mode ? " (" : "");
for (int i = 0; i < GetSize(ports); i++)
log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : "");
log("%s%s\n", ports[i], m_mode && i+1 < GetSize(ports) ? "," : "");
if (m_mode)
log(");\nendmodule\n");
};

10
passes/cmds/printattrs.cc
View file

@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass {
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str());
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str());
log("%s(* %s=%s *)\n", get_indent_str(indent), log_id(s), x.as_string());
else
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
@ -63,14 +63,14 @@ struct PrintAttrsPass : public Pass {
for (auto mod : design->selected_modules())
{
if (design->selected_whole_module(mod)) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(mod->name));
log("%s%s\n", get_indent_str(indent), log_id(mod->name));
indent += 2;
for (auto &it : mod->attributes)
log_const(it.first, it.second, indent);
}
for (auto cell : mod->selected_cells()) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(cell->name));
log("%s%s\n", get_indent_str(indent), log_id(cell->name));
indent += 2;
for (auto &it : cell->attributes)
log_const(it.first, it.second, indent);
@ -78,7 +78,7 @@ struct PrintAttrsPass : public Pass {
}
for (auto wire : mod->selected_wires()) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(wire->name));
log("%s%s\n", get_indent_str(indent), log_id(wire->name));
indent += 2;
for (auto &it : wire->attributes)
log_const(it.first, it.second, indent);

6
passes/cmds/rename.cc
View file

@ -577,7 +577,7 @@ struct RenamePass : public Pass {
new_wire_names[wire] = module->uniquify("\\" + renamed_unescaped(name));
auto new_name = new_wire_names[wire].str().substr(1);
if (VERILOG_BACKEND::id_is_verilog_escaped(new_name))
log_error("Failed to rename wire %s -> %s\n", name.c_str(), new_name.c_str());
log_error("Failed to rename wire %s -> %s\n", name, new_name);
}
for (auto cell : module->selected_cells()) {
@ -590,7 +590,7 @@ struct RenamePass : public Pass {
new_cell_names[cell] = module->uniquify("\\" + renamed_unescaped(name));
auto new_name = new_cell_names[cell].str().substr(1);
if (VERILOG_BACKEND::id_is_verilog_escaped(new_name))
log_error("Failed to rename cell %s -> %s\n", name.c_str(), new_name.c_str());
log_error("Failed to rename cell %s -> %s\n", name, new_name);
}
for (auto &it : new_wire_names)
@ -629,7 +629,7 @@ struct RenamePass : public Pass {
if (module_to_rename != nullptr) {
to_name = RTLIL::escape_id(to_name);
log("Renaming module %s to %s.\n", module_to_rename->name.c_str(), to_name.c_str());
log("Renaming module %s to %s.\n", module_to_rename->name, to_name);
design->rename(module_to_rename, to_name);
} else
log_cmd_error("Object `%s' not found!\n", from_name.c_str());

2
passes/cmds/scc.cc
View file

@ -101,7 +101,7 @@ struct SccWorker
design(design), module(module), sigmap(module)
{
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name);
return;
}

18
passes/cmds/scratchpad.cc
View file

@ -76,18 +76,18 @@ struct ScratchpadPass : public Pass {
if (args[argidx] == "-get" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier)) {
log("%s\n", design->scratchpad_get_string(identifier).c_str());
log("%s\n", design->scratchpad_get_string(identifier));
} else if (RTLIL::constpad.count(identifier)) {
log("%s\n", RTLIL::constpad.at(identifier).c_str());
log("%s\n", RTLIL::constpad.at(identifier));
} else {
log("\"%s\" not set\n", identifier.c_str());
log("\"%s\" not set\n", identifier);
}
continue;
}
if (args[argidx] == "-set" && argidx+2 < args.size()) {
string identifier = args[++argidx];
if (RTLIL::constpad.count(identifier))
log_error("scratchpad entry \"%s\" is a global constant\n", identifier.c_str());
log_error("scratchpad entry \"%s\" is a global constant\n", identifier);
string value = args[++argidx];
if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2);
design->scratchpad_set_string(identifier, value);
@ -107,9 +107,9 @@ struct ScratchpadPass : public Pass {
else if (RTLIL::constpad.count(identifier_from))
value = RTLIL::constpad.at(identifier_from);
else
log_error("\"%s\" not set\n", identifier_from.c_str());
log_error("\"%s\" not set\n", identifier_from);
if (RTLIL::constpad.count(identifier_to))
log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to.c_str());
log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to);
design->scratchpad_set_string(identifier_to, value);
continue;
}
@ -118,7 +118,7 @@ struct ScratchpadPass : public Pass {
string expected = args[++argidx];
if (expected.front() == '\"' && expected.back() == '\"') expected = expected.substr(1, expected.size() - 2);
if (design->scratchpad.count(identifier) == 0)
log_error("scratchpad entry '%s' is not defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is not defined\n", identifier);
string value = design->scratchpad_get_string(identifier);
if (value != expected) {
log_error("scratchpad entry '%s' is set to '%s' instead of the asserted '%s'\n",
@ -129,13 +129,13 @@ struct ScratchpadPass : public Pass {
if (args[argidx] == "-assert-set" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier) == 0)
log_error("scratchpad entry '%s' is not defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is not defined\n", identifier);
continue;
}
if (args[argidx] == "-assert-unset" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier) > 0)
log_error("scratchpad entry '%s' is defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is defined\n", identifier);
continue;
}
break;

16
passes/cmds/select.cc
View file

@ -632,20 +632,20 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
if (rule.cell_types.size() > 0) {
log(" cell types:");
for (auto &it : rule.cell_types)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
if (rule.port_names.size() > 0) {
log(" port names:");
for (auto &it : rule.port_names)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
}
if (limits.size() > 0) {
log(" limits:");
for (auto &it : limits)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
#endif
@ -1443,7 +1443,7 @@ struct SelectPass : public Pass {
std::ifstream f(read_file);
yosys_input_files.insert(read_file);
if (f.fail())
log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno));
log_error("Can't open '%s' for reading: %s\n", read_file, strerror(errno));
auto sel = RTLIL::Selection::EmptySelection(design);
string line;
@ -1518,7 +1518,7 @@ struct SelectPass : public Pass {
f = fopen(write_file.c_str(), "w");
yosys_output_files.insert(write_file);
if (f == nullptr)
log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno));
log_error("Can't open '%s' for writing: %s\n", write_file, strerror(errno));
}
if (work_stack.size() > 0)
design->push_selection(work_stack.back());
@ -1573,7 +1573,7 @@ struct SelectPass : public Pass {
RTLIL::Selection *sel = &work_stack.back();
sel->optimize(design);
std::string desc = describe_selection_for_assert(design, sel, true);
log_error("Assertion failed: selection is not empty:%s\n%s", sel_str.c_str(), desc.c_str());
log_error("Assertion failed: selection is not empty:%s\n%s", sel_str, desc);
}
return;
}
@ -1588,7 +1588,7 @@ struct SelectPass : public Pass {
RTLIL::Selection *sel = &work_stack.back();
sel->optimize(design);
std::string desc = describe_selection_for_assert(design, sel, true);
log_error("Assertion failed: selection is empty:%s\n%s", sel_str.c_str(), desc.c_str());
log_error("Assertion failed: selection is empty:%s\n%s", sel_str, desc);
}
return;
}
@ -1645,7 +1645,7 @@ struct SelectPass : public Pass {
if (!unset_name.empty())
{
if (!design->selection_vars.erase(unset_name))
log_error("Selection '%s' does not exist!\n", unset_name.c_str());
log_error("Selection '%s' does not exist!\n", unset_name);
return;
}

6
passes/cmds/setundef.cc
View file

@ -41,7 +41,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
if (module->count_id(name) != 0)
{
log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
log("Module %s already has such an object %s.\n", module->name, name);
name += "$";
return add_wire(module, name, width, flag_input, flag_output);
}
@ -56,7 +56,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
module->fixup_ports();
}
log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
log("Added wire %s to module %s.\n", name, module->name);
}
return wire;
@ -319,7 +319,7 @@ struct SetundefPass : public Pass {
wire = add_wire(module, name, c.width, true, false);
module->connect(RTLIL::SigSig(c, wire));
}
log("Exposing undriven wire %s as input.\n", wire->name.c_str());
log("Exposing undriven wire %s as input.\n", wire->name);
}
module->fixup_ports();
}

12
passes/cmds/show.cc
View file

@ -188,7 +188,7 @@ struct ShowWorker
if (enumerateIds) {
if (autonames.count(id) == 0) {
autonames[id] = autonames.size() + 1;
log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id.c_str());
log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id);
}
id = stringf("_%d_", autonames[id]);
} else if (abbreviateIds) {
@ -895,7 +895,7 @@ struct ShowPass : public Pass {
f.open(filename.c_str());
yosys_input_files.insert(filename);
if (f.fail())
log_error("Can't open lib file `%s'.\n", filename.c_str());
log_error("Can't open lib file `%s'.\n", filename);
RTLIL::Design *lib = new RTLIL::Design;
Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
libs.push_back(lib);
@ -907,7 +907,7 @@ struct ShowPass : public Pass {
std::string dot_file = stringf("%s.dot", prefix);
std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format);
log("Writing dot description to `%s'.\n", dot_file.c_str());
log("Writing dot description to `%s'.\n", dot_file);
FILE *f = fopen(dot_file.c_str(), "w");
if (custom_prefix)
yosys_output_files.insert(dot_file);
@ -934,7 +934,7 @@ struct ShowPass : public Pass {
#endif
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
#if !defined(YOSYS_DISABLE_SPAWN)
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
@ -954,7 +954,7 @@ struct ShowPass : public Pass {
#else
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
} else
@ -964,7 +964,7 @@ struct ShowPass : public Pass {
#else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
}

2
passes/cmds/splice.cc
View file

@ -345,7 +345,7 @@ struct SplicePass : public Pass {
for (auto module : design->selected_modules())
{
if (module->processes.size()) {
log("Skipping module %s as it contains processes.\n", module->name.c_str());
log("Skipping module %s as it contains processes.\n", module->name);
continue;
}

74
passes/cmds/stat.cc
View file

@ -285,7 +285,7 @@ struct statdata_t {
cell_area.at(cell_type).is_sequential = cell_data.is_sequential;
}
} else {
log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type.c_str(),
log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type,
(int)cell_data.double_parameter_area.size());
}
}
@ -452,22 +452,22 @@ struct statdata_t {
if (print_area) {
if (print_hierarchical) {
log(" %s %s %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), count_local_str.c_str(),
log(" %s %s %s %s %s%s\n", count_global_str, area_global_str, count_local_str,
area_local_str.c_str(), indent.c_str(), name.c_str());
} else if (print_global_only) {
log(" %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_global_str, area_global_str, indent, name);
} else {
if (count_local > 0)
log(" %s %s %s%s\n", count_local_str.c_str(), area_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_local_str, area_local_str, indent, name);
}
} else {
if (print_hierarchical) {
log(" %s %s %s%s\n", count_global_str.c_str(), count_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_global_str, count_local_str, indent, name);
} else if (print_global_only) {
log(" %s %s%s\n", count_global_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s%s\n", count_global_str, indent, name);
} else {
if (count_local > 0)
log(" %s %s%s\n", count_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s%s\n", count_local_str, indent, name);
}
}
}
@ -540,13 +540,13 @@ struct statdata_t {
if (!unknown_cell_area.empty()) {
log("\n");
for (auto cell_type : unknown_cell_area)
log(" Area for cell type %s is unknown!\n", cell_type.c_str());
log(" Area for cell type %s is unknown!\n", cell_type);
}
if (area != 0) {
log("\n");
if (print_hierarchical || print_global_only) {
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, area);
log(" of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0 * sequential_area / area);
} else {
double local_area = 0;
@ -555,7 +555,7 @@ struct statdata_t {
double local_sequential_area = 0;
for (auto &it : local_seq_area_cells_by_type)
local_sequential_area += it.second;
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), local_area);
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, local_area);
log(" of which used for sequential elements: %f (%.2f%%)\n", local_sequential_area,
100.0 * local_sequential_area / local_area);
}
@ -587,19 +587,19 @@ struct statdata_t {
if (!first_module)
log(",\n");
if (hierarchical) {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0).c_str());
log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0).c_str());
log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0).c_str());
log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0).c_str());
log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0).c_str());
log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0).c_str());
log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0).c_str());
log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0).c_str());
log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0).c_str());
log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area).c_str());
log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area).c_str());
log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area).c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0));
log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0));
log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0));
log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0));
log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0));
log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0));
log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0));
log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0));
log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0));
log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area));
log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area));
log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area));
log(" \"num_cells_by_type\": {\n");
bool first_line = true;
@ -607,7 +607,7 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(),
log(" %s: %s", json11::Json(log_id(it.first)).dump(),
json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
area_cells_by_type.at(it.first))
@ -621,7 +621,7 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(),
log(" %s: %s", json11::Json(log_id(it.first)).dump(),
json_line(0, 0, it.second,
submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0)
.c_str());
@ -640,7 +640,7 @@ struct statdata_t {
} else {
if (global_only) {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %u,\n", num_wires);
log(" \"num_wire_bits\": %u,\n", num_wire_bits);
log(" \"num_pub_wires\": %u,\n", num_pub_wires);
@ -662,20 +662,20 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
for (auto &it : num_submodules_by_type)
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
log("\n");
log(" }");
} else {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %u,\n", local_num_wires);
log(" \"num_wire_bits\": %u,\n", local_num_wire_bits);
log(" \"num_pub_wires\": %u,\n", local_num_pub_wires);
@ -697,14 +697,14 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
for (auto &it : num_submodules_by_type)
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
log("\n");
@ -824,11 +824,11 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
double value = std::stod(s);
single_parameter_area.push_back(value);
} catch (const std::exception &e) {
log_error("Failed to parse single parameter area value '%s': %s\n", s.c_str(), e.what());
log_error("Failed to parse single parameter area value '%s': %s\n", s, e.what());
}
}
if (single_parameter_area.size() == 0)
log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1].c_str());
log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1]);
// check if it is a double parameterised area
}
const LibertyAst *dar = cell->find("double_area_parameterised");
@ -857,12 +857,12 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
value = std::stod(s);
cast_sub_array.push_back(value);
} catch (const std::exception &e) {
log_error("Failed to parse double parameter area value for '%s': %s\n", s.c_str(), e.what());
log_error("Failed to parse double parameter area value for '%s': %s\n", s, e.what());
}
}
double_parameter_area.push_back(cast_sub_array);
if (cast_sub_array.size() == 0)
log_error("double paramter array has size 0: %s\n", s.c_str());
log_error("double paramter array has size 0: %s\n", s);
}
}
const LibertyAst *par = cell->find("port_names");
@ -973,10 +973,10 @@ struct StatPass : public Pass {
if (json_mode) {
log("{\n");
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str());
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump());
std::stringstream invocation;
std::copy(args.begin(), args.end(), std::ostream_iterator<std::string>(invocation, " "));
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str());
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump());
log(" \"modules\": {\n");
}

4
passes/cmds/timeest.cc
View file

@ -322,7 +322,7 @@ struct EstimateSta {
std::string src_attr = cell->get_src_attribute();
cell_src = stringf(" source: %s", src_attr);
}
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src.c_str());
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src);
printed.insert(cell);
}
} else {
@ -333,7 +333,7 @@ struct EstimateSta {
std::string src_attr = bit.wire->get_src_attribute();
wire_src = stringf(" source: %s", src_attr);
}
log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src.c_str(), levels[node]);
log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src, levels[node]);
}
}

8
passes/cmds/viz.cc
View file

@ -988,7 +988,7 @@ struct VizPass : public Pass {
if (custom_prefix)
yosys_output_files.insert(dot_file);
log("Writing dot description to `%s'.\n", dot_file.c_str());
log("Writing dot description to `%s'.\n", dot_file);
FILE *f = nullptr;
auto open_dot_file = [&]() {
if (f != nullptr) return;
@ -1028,7 +1028,7 @@ struct VizPass : public Pass {
#endif
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
#if !defined(YOSYS_DISABLE_SPAWN)
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
@ -1047,7 +1047,7 @@ struct VizPass : public Pass {
#else
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
} else
@ -1057,7 +1057,7 @@ struct VizPass : public Pass {
#else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
}

4
passes/cmds/wrapcell.cc
View file

@ -59,7 +59,7 @@ std::optional<std::string> format_with_params(std::string fmt, const dict<IdStri
auto beg = it;
while (it != fmt.end() && *it != '}') it++;
if (it == fmt.end()) {
log("Unclosed curly brackets in format string '%s'\n", fmt.c_str());
log("Unclosed curly brackets in format string '%s'\n", fmt);
return {};
}
@ -70,7 +70,7 @@ std::optional<std::string> format_with_params(std::string fmt, const dict<IdStri
} else {
auto id = RTLIL::escape_id(std::string(beg, it));
if (!parameters.count(id)) {
log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt);
return {};
}

4
passes/fsm/fsm_expand.cc
View file

@ -140,7 +140,7 @@ struct FsmExpand
{
optimze_as_needed();
log(" merging %s cell %s.\n", cell->type.c_str(), cell->name.c_str());
log(" merging %s cell %s.\n", cell->type, cell->name);
merged_set.insert(cell);
already_optimized = false;
@ -243,7 +243,7 @@ struct FsmExpand
void execute()
{
log("\n");
log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name, module->name);
already_optimized = false;
limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int();

2
passes/fsm/fsm_export.cc
View file

@ -76,7 +76,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
if (!kiss_file.is_open()) {
log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str());
log_error("Could not open file \"%s\" with write access.\n", kiss_name);
}
fsm_data.copy_from_cell(cell);

6
passes/fsm/fsm_extract.cc
View file

@ -71,7 +71,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
{
RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, cell->name);
return false;
}
@ -255,7 +255,7 @@ undef_bit_in_next_state:
static void extract_fsm(RTLIL::Wire *wire)
{
log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str());
log("Extracting FSM `%s' from module `%s'.\n", wire->name, module->name);
// get input and output signals for state ff
@ -274,7 +274,7 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
continue;
log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
log(" found %s cell for state register: %s\n", cell->type, cell->name);
RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
clk = cell->getPort(ID::CLK);

2
passes/fsm/fsm_map.cc
View file

@ -156,7 +156,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{
log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name.c_str(), module->name.c_str());
log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name, module->name);
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);

2
passes/fsm/fsm_opt.cc
View file

@ -293,7 +293,7 @@ struct FsmOpt
FsmOpt(RTLIL::Cell *cell, RTLIL::Module *module)
{
log("Optimizing FSM `%s' from module `%s'.\n", cell->name.c_str(), module->name.c_str());
log("Optimizing FSM `%s' from module `%s'.\n", cell->name, module->name);
fsm_data.copy_from_cell(cell);
this->cell = cell;

16
passes/fsm/fsm_recode.cc
View file

@ -56,15 +56,15 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
{
std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto";
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name, module->name, encoding);
if (encoding != "none" && encoding != "user" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") {
log(" unknown encoding `%s': using auto instead.\n", encoding.c_str());
log(" unknown encoding `%s': using auto instead.\n", encoding);
encoding = "auto";
}
if (encoding == "none" || encoding == "user") {
log(" nothing to do for encoding `%s'.\n", encoding.c_str());
log(" nothing to do for encoding `%s'.\n", encoding);
return;
}
@ -79,7 +79,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
encoding = default_encoding;
else
encoding = GetSize(fsm_data.state_table) < 32 ? "one-hot" : "binary";
log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str());
log(" mapping auto encoding to `%s` for this FSM.\n", encoding);
}
if (encoding == "one-hot") {
@ -93,7 +93,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
}
fsm_data.state_bits = new_num_state_bits;
} else
log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
log_error("FSM encoding `%s' is not supported!\n", encoding);
if (encfile)
fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
@ -113,7 +113,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
} else
log_abort();
log(" %s -> %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str());
log(" %s -> %s\n", fsm_data.state_table[i].as_string(), new_code.as_string());
if (encfile)
fprintf(encfile, ".map %s %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str());
fsm_data.state_table[i] = new_code;
@ -165,13 +165,13 @@ struct FsmRecodePass : public Pass {
if (arg == "-fm_set_fsm_file" && argidx+1 < args.size() && fm_set_fsm_file == NULL) {
fm_set_fsm_file = fopen(args[++argidx].c_str(), "w");
if (fm_set_fsm_file == NULL)
log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno));
log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx], strerror(errno));
continue;
}
if (arg == "-encfile" && argidx+1 < args.size() && encfile == NULL) {
encfile = fopen(args[++argidx].c_str(), "w");
if (encfile == NULL)
log_error("Can't open encfile `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno));
log_error("Can't open encfile `%s' for writing: %s\n", args[argidx], strerror(errno));
continue;
}
if (arg == "-encoding" && argidx+1 < args.size() && default_encoding.empty()) {

2
passes/fsm/fsmdata.h
View file

@ -134,7 +134,7 @@ struct FsmData
{
log("-------------------------------------\n");
log("\n");
log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
log(" Information on FSM %s (%s):\n", cell->name, cell->parameters[ID::NAME].decode_string());
log("\n");
log(" Number of input signals: %3d\n", num_inputs);
log(" Number of output signals: %3d\n", num_outputs);

12
passes/hierarchy/hierarchy.cc
View file

@ -59,7 +59,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
std::set<RTLIL::IdString> portnames;
std::set<RTLIL::IdString> parameters;
std::map<RTLIL::IdString, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
log("Generate module for cell type %s:\n", celltype);
for (auto mod : design->modules())
for (auto cell : mod->cells())
@ -605,9 +605,9 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::
return;
if (indent == 0)
log("Top module: %s\n", mod->name.c_str());
log("Top module: %s\n", mod->name);
else if (!mod->get_blackbox_attribute())
log("Used module: %*s%s\n", indent, "", mod->name.c_str());
log("Used module: %*s%s\n", indent, "", mod->name);
used.insert(mod);
for (auto cell : mod->cells()) {
@ -647,7 +647,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
for (auto mod : del_modules) {
if (!purge_lib && mod->get_blackbox_attribute())
continue;
log("Removing unused module `%s'.\n", mod->name.c_str());
log("Removing unused module `%s'.\n", mod->name);
design->remove(mod);
del_counter++;
}
@ -873,11 +873,11 @@ struct HierarchyPass : public Pass {
log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output");
if (decl.index >= 1)
log(" [at position %d]", decl.index);
log(" %s\n", decl.portname.c_str());
log(" %s\n", decl.portname);
generate_ports.push_back(decl);
continue;
is_celltype:
log("Celltype: %s\n", args[argidx].c_str());
log("Celltype: %s\n", args[argidx]);
generate_cells.push_back(RTLIL::unescape_id(args[argidx]));
}
continue;

16
passes/hierarchy/submod.cc
View file

@ -87,7 +87,7 @@ struct SubmodWorker
void handle_submodule(SubModule &submod)
{
log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str());
log("Creating submodule %s (%s) of module %s.\n", submod.name, submod.full_name, module->name);
wire_flags.clear();
for (RTLIL::Cell *cell : submod.cells) {
@ -192,13 +192,13 @@ struct SubmodWorker
}
if (new_wire->port_input && new_wire->port_output)
log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: inout %s\n", wire->name, new_wire->name);
else if (new_wire->port_input)
log(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: input %s\n", wire->name, new_wire->name);
else if (new_wire->port_output)
log(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: output %s\n", wire->name, new_wire->name);
else
log(" signal %s: internal\n", wire->name.c_str());
log(" signal %s: internal\n", wire->name);
flags.new_wire = new_wire;
}
@ -214,7 +214,7 @@ struct SubmodWorker
log_assert(wire_flags.count(bit.wire) > 0);
bit.wire = wire_flags.at(bit.wire).new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
log(" cell %s (%s)\n", new_cell->name, new_cell->type);
if (!copy_mode)
module->remove(cell);
}
@ -250,12 +250,12 @@ struct SubmodWorker
return;
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name);
return;
}
if (module->memories.size() > 0) {
log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name);
return;
}

124
passes/memory/memlib.cc
View file

@ -134,7 +134,7 @@ struct Parser {
rewrite_filename(filename);
infile.open(filename);
if (infile.fail()) {
log_error("failed to open %s\n", filename.c_str());
log_error("failed to open %s\n", filename);
}
parse();
infile.close();
@ -181,14 +181,14 @@ struct Parser {
void eat_token(std::string expected) {
std::string token = get_token();
if (token != expected) {
log_error("%s:%d: expected `%s`, got `%s`.\n", filename.c_str(), line_number, expected.c_str(), token.c_str());
log_error("%s:%d: expected `%s`, got `%s`.\n", filename, line_number, expected, token);
}
}
IdString get_id() {
std::string token = get_token();
if (token.empty() || (token[0] != '$' && token[0] != '\\')) {
log_error("%s:%d: expected id string, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected id string, got `%s`.\n", filename, line_number, token);
}
return IdString(token);
}
@ -203,14 +203,14 @@ struct Parser {
if (!isalnum(c) && c != '_')
valid = false;
if (!valid)
log_error("%s:%d: expected name, got `%s`.\n", filename.c_str(), line_number, res.c_str());
log_error("%s:%d: expected name, got `%s`.\n", filename, line_number, res);
return res;
}
std::string get_string() {
std::string token = get_token();
if (token.size() < 2 || token[0] != '"' || token[token.size()-1] != '"') {
log_error("%s:%d: expected string, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected string, got `%s`.\n", filename, line_number, token);
}
return token.substr(1, token.size()-2);
}
@ -225,7 +225,7 @@ struct Parser {
char *endptr;
long res = strtol(token.c_str(), &endptr, 0);
if (token.empty() || *endptr || res > INT_MAX) {
log_error("%s:%d: expected int, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected int, got `%s`.\n", filename, line_number, token);
}
return res;
}
@ -235,7 +235,7 @@ struct Parser {
char *endptr;
double res = strtod(token.c_str(), &endptr);
if (token.empty() || *endptr) {
log_error("%s:%d: expected float, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected float, got `%s`.\n", filename, line_number, token);
}
return res;
}
@ -248,7 +248,7 @@ struct Parser {
void get_semi() {
std::string token = get_token();
if (token != ";") {
log_error("%s:%d: expected `;`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `;`, got `%s`.\n", filename, line_number, token);
}
}
@ -387,7 +387,7 @@ struct Parser {
exit_portoption();
} else if (token == "clock") {
if (port.kind == PortKind::Ar) {
log_error("%s:%d: `clock` not allowed in async read port.\n", filename.c_str(), line_number);
log_error("%s:%d: `clock` not allowed in async read port.\n", filename, line_number);
}
ClockDef def;
token = get_token();
@ -398,7 +398,7 @@ struct Parser {
} else if (token == "negedge") {
def.kind = ClkPolKind::Negedge;
} else {
log_error("%s:%d: expected `posedge`, `negedge`, or `anyedge`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `posedge`, `negedge`, or `anyedge`, got `%s`.\n", filename, line_number, token);
}
if (peek_string()) {
def.name = get_string();
@ -407,13 +407,13 @@ struct Parser {
add_cap(port.clock, def);
} else if (token == "clken") {
if (port.kind == PortKind::Ar) {
log_error("%s:%d: `clken` not allowed in async read port.\n", filename.c_str(), line_number);
log_error("%s:%d: `clken` not allowed in async read port.\n", filename, line_number);
}
get_semi();
add_cap(port.clken, {});
} else if (token == "wrbe_separate") {
if (port.kind == PortKind::Ar || port.kind == PortKind::Sr) {
log_error("%s:%d: `wrbe_separate` not allowed in read port.\n", filename.c_str(), line_number);
log_error("%s:%d: `wrbe_separate` not allowed in read port.\n", filename, line_number);
}
get_semi();
add_cap(port.wrbe_separate, {});
@ -424,14 +424,14 @@ struct Parser {
if (token == "tied") {
get_token();
if (!is_rw)
log_error("%s:%d: `tied` only makes sense for read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `tied` only makes sense for read+write ports.\n", filename, line_number);
while (peek_int())
def.wr_widths.push_back(get_int());
def.tied = true;
} else if (token == "mix") {
get_token();
if (!is_rw)
log_error("%s:%d: `mix` only makes sense for read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `mix` only makes sense for read+write ports.\n", filename, line_number);
while (peek_int())
def.wr_widths.push_back(get_int());
def.rd_widths = def.wr_widths;
@ -439,7 +439,7 @@ struct Parser {
} else if (token == "rd") {
get_token();
if (!is_rw)
log_error("%s:%d: `rd` only makes sense for read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `rd` only makes sense for read+write ports.\n", filename, line_number);
do {
def.rd_widths.push_back(get_int());
} while (peek_int());
@ -451,7 +451,7 @@ struct Parser {
} else if (token == "wr") {
get_token();
if (!is_rw)
log_error("%s:%d: `wr` only makes sense for read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `wr` only makes sense for read+write ports.\n", filename, line_number);
do {
def.wr_widths.push_back(get_int());
} while (peek_int());
@ -470,12 +470,12 @@ struct Parser {
add_cap(port.width, def);
} else if (token == "rden") {
if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw)
log_error("%s:%d: `rden` only allowed on sync read ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `rden` only allowed on sync read ports.\n", filename, line_number);
get_semi();
add_cap(port.rden, {});
} else if (token == "rdwr") {
if (port.kind != PortKind::Srsw)
log_error("%s:%d: `rdwr` only allowed on sync read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `rdwr` only allowed on sync read+write ports.\n", filename, line_number);
RdWrKind kind;
token = get_token();
if (token == "undefined") {
@ -489,13 +489,13 @@ struct Parser {
} else if (token == "new_only") {
kind = RdWrKind::NewOnly;
} else {
log_error("%s:%d: expected `undefined`, `new`, `old`, `new_only`, or `no_change`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `undefined`, `new`, `old`, `new_only`, or `no_change`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(port.rdwr, kind);
} else if (token == "rdinit") {
if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw)
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token);
ResetValKind kind;
token = get_token();
if (token == "none") {
@ -507,13 +507,13 @@ struct Parser {
} else if (token == "no_undef") {
kind = ResetValKind::NoUndef;
} else {
log_error("%s:%d: expected `none`, `zero`, `any`, or `no_undef`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `none`, `zero`, `any`, or `no_undef`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(port.rdinit, kind);
} else if (token == "rdarst") {
if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw)
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token);
ResetValKind kind;
token = get_token();
if (token == "none") {
@ -527,13 +527,13 @@ struct Parser {
} else if (token == "init") {
kind = ResetValKind::Init;
} else {
log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(port.rdarst, kind);
} else if (token == "rdsrst") {
if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw)
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token);
SrstDef def;
token = get_token();
if (token == "none") {
@ -547,7 +547,7 @@ struct Parser {
} else if (token == "init") {
def.val = ResetValKind::Init;
} else {
log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename, line_number, token);
}
if (def.val == ResetValKind::None) {
def.kind = SrstKind::None;
@ -560,7 +560,7 @@ struct Parser {
} else if (token == "gated_rden") {
def.kind = SrstKind::GatedRdEn;
} else {
log_error("%s:%d: expected `ungated`, `gated_clken` or `gated_rden`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `ungated`, `gated_clken` or `gated_rden`, got `%s`.\n", filename, line_number, token);
}
}
def.block_wr = false;
@ -572,14 +572,14 @@ struct Parser {
add_cap(port.rdsrst, def);
} else if (token == "wrprio") {
if (port.kind == PortKind::Ar || port.kind == PortKind::Sr)
log_error("%s:%d: `wrprio` only allowed on write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `wrprio` only allowed on write ports.\n", filename, line_number);
do {
add_cap(port.wrprio, get_string());
} while (peek_string());
get_semi();
} else if (token == "wrtrans") {
if (port.kind == PortKind::Ar || port.kind == PortKind::Sr)
log_error("%s:%d: `wrtrans` only allowed on write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `wrtrans` only allowed on write ports.\n", filename, line_number);
token = peek_token();
RawWrTransDef def;
if (token == "all") {
@ -595,7 +595,7 @@ struct Parser {
} else if (token == "old") {
def.kind = WrTransKind::Old;
} else {
log_error("%s:%d: expected `new` or `old`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `new` or `old`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(port.wrtrans, def);
@ -609,9 +609,9 @@ struct Parser {
get_semi();
add_cap(port.optional_rw, {});
} else if (token == "") {
log_error("%s:%d: unexpected EOF while parsing port item.\n", filename.c_str(), line_number);
log_error("%s:%d: unexpected EOF while parsing port item.\n", filename, line_number);
} else {
log_error("%s:%d: unknown port-level item `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: unknown port-level item `%s`.\n", filename, line_number, token);
}
}
@ -646,14 +646,14 @@ struct Parser {
} else if (token == "abits") {
int val = get_int();
if (val < 0)
log_error("%s:%d: abits %d nagative.\n", filename.c_str(), line_number, val);
log_error("%s:%d: abits %d nagative.\n", filename, line_number, val);
get_semi();
add_cap(ram.abits, val);
} else if (token == "width") {
WidthsDef def;
int w = get_int();
if (w <= 0)
log_error("%s:%d: width %d not positive.\n", filename.c_str(), line_number, w);
log_error("%s:%d: width %d not positive.\n", filename, line_number, w);
def.widths.push_back(w);
def.mode = WidthMode::Single;
get_semi();
@ -664,9 +664,9 @@ struct Parser {
do {
int w = get_int();
if (w <= 0)
log_error("%s:%d: width %d not positive.\n", filename.c_str(), line_number, w);
log_error("%s:%d: width %d not positive.\n", filename, line_number, w);
if (w < last * 2)
log_error("%s:%d: width %d smaller than %d required for progression.\n", filename.c_str(), line_number, w, last * 2);
log_error("%s:%d: width %d smaller than %d required for progression.\n", filename, line_number, w, last * 2);
last = w;
def.widths.push_back(w);
} while(peek_int());
@ -676,7 +676,7 @@ struct Parser {
} else if (token == "per_port") {
def.mode = WidthMode::PerPort;
} else {
log_error("%s:%d: expected `global`, or `per_port`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `global`, or `per_port`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(ram.widths, def);
@ -702,7 +702,7 @@ struct Parser {
} else if (token == "byte") {
int val = get_int();
if (val <= 0)
log_error("%s:%d: byte width %d not positive.\n", filename.c_str(), line_number, val);
log_error("%s:%d: byte width %d not positive.\n", filename, line_number, val);
add_cap(ram.byte, val);
get_semi();
} else if (token == "init") {
@ -717,7 +717,7 @@ struct Parser {
} else if (token == "none") {
kind = MemoryInitKind::None;
} else {
log_error("%s:%d: expected `zero`, `any`, `none`, or `no_undef`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `zero`, `any`, `none`, or `no_undef`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(ram.init, kind);
@ -743,7 +743,7 @@ struct Parser {
} else if (token == "srsw") {
port.kind = PortKind::Srsw;
} else {
log_error("%s:%d: expected `ar`, `sr`, `sw`, `arsw`, or `srsw`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `ar`, `sr`, `sw`, `arsw`, or `srsw`, got `%s`.\n", filename, line_number, token);
}
do {
port.names.push_back(get_string());
@ -752,9 +752,9 @@ struct Parser {
if (active)
add_cap(ram.ports, port);
} else if (token == "") {
log_error("%s:%d: unexpected EOF while parsing ram item.\n", filename.c_str(), line_number);
log_error("%s:%d: unexpected EOF while parsing ram item.\n", filename, line_number);
} else {
log_error("%s:%d: unknown ram-level item `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: unknown ram-level item `%s`.\n", filename, line_number, token);
}
}
@ -787,7 +787,7 @@ struct Parser {
} else if (token == "huge") {
ram.kind = RamKind::Huge;
} else {
log_error("%s:%d: expected `distributed`, `block`, or `huge`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `distributed`, `block`, or `huge`, got `%s`.\n", filename, line_number, token);
}
ram.id = get_id();
parse_ram_block();
@ -795,9 +795,9 @@ struct Parser {
compile_ram(orig_line);
}
} else if (token == "") {
log_error("%s:%d: unexpected EOF while parsing top item.\n", filename.c_str(), line_number);
log_error("%s:%d: unexpected EOF while parsing top item.\n", filename, line_number);
} else {
log_error("%s:%d: unknown top-level item `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: unknown top-level item `%s`.\n", filename, line_number, token);
}
}
@ -816,7 +816,7 @@ struct Parser {
if (!opts_ok(cap.portopts, portopts))
continue;
if (res)
log_error("%s:%d: duplicate %s cap.\n", filename.c_str(), line_number, name);
log_error("%s:%d: duplicate %s cap.\n", filename, line_number, name);
res = &cap.val;
}
return res;
@ -860,7 +860,7 @@ struct Parser {
} else {
const ClockDef *cdef = find_single_cap(pdef.clock, cram.options, portopts, "clock");
if (!cdef)
log_error("%s:%d: missing clock capability.\n", filename.c_str(), orig_line);
log_error("%s:%d: missing clock capability.\n", filename, orig_line);
var.clk_pol = cdef->kind;
if (cdef->name.empty()) {
var.clk_shared = -1;
@ -876,7 +876,7 @@ struct Parser {
} else {
var.clk_shared = it->second;
if (cram.shared_clocks[var.clk_shared].anyedge != anyedge) {
log_error("%s:%d: named clock \"%s\" used with both posedge/negedge and anyedge clocks.\n", filename.c_str(), orig_line, cdef->name.c_str());
log_error("%s:%d: named clock \"%s\" used with both posedge/negedge and anyedge clocks.\n", filename, orig_line, cdef->name);
}
}
}
@ -885,7 +885,7 @@ struct Parser {
const PortWidthDef *wdef = find_single_cap(pdef.width, cram.options, portopts, "width");
if (wdef) {
if (cram.width_mode != WidthMode::PerPort)
log_error("%s:%d: per-port width doesn't make sense for tied dbits.\n", filename.c_str(), orig_line);
log_error("%s:%d: per-port width doesn't make sense for tied dbits.\n", filename, orig_line);
compile_widths(var, cram.dbits, *wdef);
} else {
var.width_tied = true;
@ -908,9 +908,9 @@ struct Parser {
var.rdsrstmode = srv->kind;
var.rdsrst_block_wr = srv->block_wr;
if (srv->kind == SrstKind::GatedClkEn && !var.clk_en)
log_error("%s:%d: `gated_clken` used without `clken`.\n", filename.c_str(), orig_line);
log_error("%s:%d: `gated_clken` used without `clken`.\n", filename, orig_line);
if (srv->kind == SrstKind::GatedRdEn && !var.rd_en)
log_error("%s:%d: `gated_rden` used without `rden`.\n", filename.c_str(), orig_line);
log_error("%s:%d: `gated_rden` used without `rden`.\n", filename, orig_line);
} else {
var.rdsrstval = ResetValKind::None;
var.rdsrstmode = SrstKind::None;
@ -918,13 +918,13 @@ struct Parser {
}
if (var.rdarstval == ResetValKind::Init || var.rdsrstval == ResetValKind::Init) {
if (var.rdinitval != ResetValKind::Any && var.rdinitval != ResetValKind::NoUndef) {
log_error("%s:%d: reset value `init` has to be paired with `any` or `no_undef` initial value.\n", filename.c_str(), orig_line);
log_error("%s:%d: reset value `init` has to be paired with `any` or `no_undef` initial value.\n", filename, orig_line);
}
}
}
var.wrbe_separate = find_single_cap(pdef.wrbe_separate, cram.options, portopts, "wrbe_separate");
if (var.wrbe_separate && cram.byte == 0) {
log_error("%s:%d: `wrbe_separate` used without `byte`.\n", filename.c_str(), orig_line);
log_error("%s:%d: `wrbe_separate` used without `byte`.\n", filename, orig_line);
}
for (auto &def: pdef.wrprio) {
if (!opts_ok(def.opts, cram.options))
@ -948,18 +948,18 @@ struct Parser {
grp.variants.push_back(var);
}
if (grp.variants.empty()) {
log_error("%s:%d: all port option combinations are forbidden.\n", filename.c_str(), orig_line);
log_error("%s:%d: all port option combinations are forbidden.\n", filename, orig_line);
}
cram.port_groups.push_back(grp);
}
void compile_ram(int orig_line) {
if (ram.abits.empty())
log_error("%s:%d: `dims` capability should be specified.\n", filename.c_str(), orig_line);
log_error("%s:%d: `dims` capability should be specified.\n", filename, orig_line);
if (ram.widths.empty())
log_error("%s:%d: `widths` capability should be specified.\n", filename.c_str(), orig_line);
log_error("%s:%d: `widths` capability should be specified.\n", filename, orig_line);
if (ram.ports.empty())
log_error("%s:%d: at least one port group should be specified.\n", filename.c_str(), orig_line);
log_error("%s:%d: at least one port group should be specified.\n", filename, orig_line);
for (auto opts: make_opt_combinations(ram.opts)) {
bool forbidden = false;
for (auto &fdef: ram.forbid) {
@ -1003,7 +1003,7 @@ struct Parser {
const int *byte = find_single_cap(ram.byte, opts, Options(), "byte");
cram.byte = byte ? *byte : 0;
if (GetSize(cram.dbits) - 1 > cram.abits)
log_error("%s:%d: abits %d too small for dbits progression.\n", filename.c_str(), line_number, cram.abits);
log_error("%s:%d: abits %d too small for dbits progression.\n", filename, line_number, cram.abits);
validate_byte(widths->widths, cram.byte);
const MemoryInitKind *ik = find_single_cap(ram.init, opts, Options(), "init");
cram.init = ik ? *ik : MemoryInitKind::None;
@ -1037,18 +1037,18 @@ struct Parser {
if (widths[0] % byte == 0) {
for (int j = 1; j < GetSize(widths); j++)
if (widths[j] % byte != 0)
log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename.c_str(), line_number, byte);
log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename, line_number, byte);
return;
}
for (int i = 0; i < GetSize(widths); i++) {
if (widths[i] == byte) {
for (int j = i + 1; j < GetSize(widths); j++)
if (widths[j] % byte != 0)
log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename.c_str(), line_number, byte);
log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename, line_number, byte);
return;
}
}
log_error("%s:%d: byte width %d invalid for dbits.\n", filename.c_str(), line_number, byte);
log_error("%s:%d: byte width %d invalid for dbits.\n", filename, line_number, byte);
}
void compile_widths(PortVariant &var, const std::vector<int> &widths, const PortWidthDef &width) {
@ -1073,13 +1073,13 @@ struct Parser {
if (dbits[i] == widths[0]) {
for (int j = 0; j < GetSize(widths); j++) {
if (i+j >= GetSize(dbits) || dbits[i+j] != widths[j]) {
log_error("%s:%d: port width %d doesn't match dbits progression.\n", filename.c_str(), line_number, widths[j]);
log_error("%s:%d: port width %d doesn't match dbits progression.\n", filename, line_number, widths[j]);
}
}
return {i, i + GetSize(widths) - 1};
}
}
log_error("%s:%d: port width %d invalid for dbits.\n", filename.c_str(), line_number, widths[0]);
log_error("%s:%d: port width %d invalid for dbits.\n", filename, line_number, widths[0]);
}
void parse() {

4
passes/memory/memory_bram.cc
View file

@ -369,7 +369,7 @@ struct rules_t
attr_icase = false;
if (infile.fail())
log_error("Can't open rules file `%s'.\n", filename.c_str());
log_error("Can't open rules file `%s'.\n", filename);
while (next_line())
{
@ -1020,7 +1020,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
log(" Properties:");
for (auto &it : match_properties)
log(" %s=%d", it.first.c_str(), it.second);
log(" %s=%d", it.first, it.second);
log("\n");
pool<pair<IdString, int>> failed_brams;

4
passes/memory/memory_dff.cc
View file

@ -334,7 +334,7 @@ struct MemoryDffWorker
void handle_rd_port(Mem &mem, QuickConeSat &qcsat, int idx)
{
auto &port = mem.rd_ports[idx];
log("Checking read port `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str());
log("Checking read port `%s'[%d] in module `%s': ", mem.memid, idx, module->name);
std::vector<MuxData> muxdata;
SigSpec data = walk_muxes(port.data, muxdata);
@ -554,7 +554,7 @@ struct MemoryDffWorker
void handle_rd_port_addr(Mem &mem, int idx)
{
auto &port = mem.rd_ports[idx];
log("Checking read port address `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str());
log("Checking read port address `%s'[%d] in module `%s': ", mem.memid, idx, module->name);
FfData ff;
pool<std::pair<Cell *, int>> bits;

10
passes/memory/memory_libmap.cc
View file

@ -548,20 +548,20 @@ void MemMapping::determine_style() {
// Nothing.
} else if (val_s == "logic" || val_s == "registers") {
kind = RamKind::Logic;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
} else if (val_s == "distributed") {
kind = RamKind::Distributed;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
} else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") {
kind = RamKind::Block;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
} else if (val_s == "huge" || val_s == "ultra") {
kind = RamKind::Huge;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
} else {
kind = RamKind::NotLogic;
style = val_s;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid), val_s.c_str());
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid), val_s);
}
return;
}

2
passes/memory/memory_map.cc
View file

@ -192,7 +192,7 @@ struct MemoryMapWorker
}
}
log("Mapping memory %s in module %s:\n", mem.memid.c_str(), module->name.c_str());
log("Mapping memory %s in module %s:\n", mem.memid, module->name);
int abits = ceil_log2(mem.size);
std::vector<RTLIL::SigSpec> data_reg_in(1 << abits);

4
passes/memory/memory_share.cc
View file

@ -371,9 +371,9 @@ struct MemoryShareWorker
ports += std::to_string(idx);
}
if (!some_port.clk_enable) {
log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports.c_str());
log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports);
} else {
log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports.c_str());
log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports);
}
// Okay, time to actually run the SAT solver.

2
passes/opt/opt_clean.cc
View file

@ -597,7 +597,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit)
{
if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name.c_str());
log("Finding unused cells or wires in module %s..\n", module->name);
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())

2
passes/opt/opt_lut.cc
View file

@ -99,7 +99,7 @@ struct OptLutWorker
}
for (int i = 0; i < GetSize(dlogic); i++)
{
log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type.c_str(), i, dlogic_counts[i]);
log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type, i, dlogic_counts[i]);
}
}

2
passes/opt/opt_merge.cc
View file

@ -228,7 +228,7 @@ struct OptMergeWorker
ct.cell_types.erase(ID($allseq));
ct.cell_types.erase(ID($allconst));
log("Finding identical cells in module `%s'.\n", module->name.c_str());
log("Finding identical cells in module `%s'.\n", module->name);
assign_map.set(module);
initvals.set(&assign_map, module);

2
passes/opt/opt_muxtree.cc
View file

@ -205,7 +205,7 @@ struct OptMuxtreeWorker
OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) :
design(design), module(module), assign_map(module), removed_count(0)
{
log("Running muxtree optimizer on module %s..\n", module->name.c_str());
log("Running muxtree optimizer on module %s..\n", module->name);
log(" Creating internal representation of mux trees.\n");

14
passes/opt/opt_reduce.cc
View file

@ -93,7 +93,7 @@ struct OptReduceWorker
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a));
did_something = true;
total_count++;
}
@ -155,7 +155,7 @@ struct OptReduceWorker
}
if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) {
log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::B, new_sig_b);
@ -242,7 +242,7 @@ struct OptReduceWorker
}
if (new_sig_s.size() != sig_s.size()) {
log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::A, new_sig_a);
@ -308,7 +308,7 @@ struct OptReduceWorker
if (new_sig_s.size() == sig_s.size() && sig_s.size() > 0)
return;
log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
@ -388,7 +388,7 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
if (cell->type != ID($bmux)) {
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
@ -479,7 +479,7 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
@ -515,7 +515,7 @@ struct OptReduceWorker
OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) :
design(design), module(module), assign_map(module)
{
log(" Optimizing cells in module %s.\n", module->name.c_str());
log(" Optimizing cells in module %s.\n", module->name);
total_count = 0;
did_something = true;

10
passes/opt/rmports.cc
View file

@ -64,7 +64,7 @@ struct RmportsPassPass : public Pass {
void CleanupModule(Module *module, dict<IdString, pool<IdString>> &removed_ports)
{
log("Removing now-unused cell ports in module %s\n", module->name.c_str());
log("Removing now-unused cell ports in module %s\n", module->name);
auto cells = module->cells();
for(auto cell : cells)
@ -88,7 +88,7 @@ struct RmportsPassPass : public Pass {
void ScanModule(Module* module, dict<IdString, pool<IdString>> &removed_ports)
{
log("Finding unconnected ports in module %s\n", module->name.c_str());
log("Finding unconnected ports in module %s\n", module->name);
pool<IdString> used_ports;
@ -113,7 +113,7 @@ struct RmportsPassPass : public Pass {
if( (w1 == NULL) || (w2 == NULL) )
continue;
//log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str());
//log(" conn %s, %s\n", w1->name, w2->name);
if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) )
used_ports.insert(w1->name);
@ -136,7 +136,7 @@ struct RmportsPassPass : public Pass {
if(sig == NULL)
continue;
// log(" sig %s\n", sig->name.c_str());
// log(" sig %s\n", sig->name);
if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
used_ports.insert(sig->name);
}
@ -155,7 +155,7 @@ struct RmportsPassPass : public Pass {
// Print the ports out as we go through them
for(auto port : unused_ports)
{
log(" removing unused port %s\n", port.c_str());
log(" removing unused port %s\n", port);
removed_ports[module->name].insert(port);
// Remove from ports list

4
passes/pmgen/pmgen.py
View file

@ -454,7 +454,7 @@ with open(outfile, "w") as f:
print(" SigSpec port(Cell *cell, IdString portname) {", file=f)
print(" try {", file=f)
print(" return sigmap(cell->getPort(portname));", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname.c_str()); }", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f)
print(" }", file=f)
print("", file=f)
print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f)
@ -465,7 +465,7 @@ with open(outfile, "w") as f:
print(" Const param(Cell *cell, IdString paramname) {", file=f)
print(" try {", file=f)
print(" return cell->getParam(paramname);", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname.c_str()); }", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname); }", file=f)
print(" }", file=f)
print("", file=f)
print(" Const param(Cell *cell, IdString paramname, const Const& defval) {", file=f)

4
passes/proc/proc_arst.cc
View file

@ -204,7 +204,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
bool polarity = sync->type == RTLIL::SyncType::STp;
if (check_signal(mod, root_sig, sync->signal, polarity)) {
if (edge_syncs.size() > 1) {
log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name);
sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0;
arst_syncs.push_back(sync);
edge_syncs.erase(it);
@ -223,7 +223,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
sync->mem_write_actions.clear();
eliminate_const(mod, &proc->root_case, root_sig, polarity);
} else {
log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name);
eliminate_const(mod, &proc->root_case, root_sig, !polarity);
}
did_something = true;

4
passes/proc/proc_clean.cc
View file

@ -171,7 +171,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool
proc_clean_case(&proc->root_case, did_something, count, -1);
}
if (count > 0 && !quiet)
log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name.c_str(), proc->name.c_str());
log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name, proc->name);
total_count += count;
}
@ -215,7 +215,7 @@ struct ProcCleanPass : public Pass {
if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 &&
proc->root_case.actions.size() == 0) {
if (!quiet)
log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str());
log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name);
delme.push_back(proc);
}
}

6
passes/proc/proc_dff.cc
View file

@ -106,7 +106,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
cell->setPort(ID::CLK, clk);
cell->setPort(ID::ALOAD, set);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type, cell->name,
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
}
@ -136,9 +136,9 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
cell->setPort(ID::CLK, clk);
if (!clk.empty())
log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
log(" created %s cell `%s' with %s edge clock", cell->type, cell->name, clk_polarity ? "positive" : "negative");
else
log(" created %s cell `%s' with global clock", cell->type.c_str(), cell->name.c_str());
log(" created %s cell `%s' with global clock", cell->type, cell->name);
if (arst)
log(" and %s level reset", arst_polarity ? "positive" : "negative");
log(".\n");

2
passes/proc/proc_dlatch.cc
View file

@ -404,7 +404,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
for (auto &bit : lhs) {
State val = db.initvals(bit);
if (db.initvals(bit) != State::Sx) {
log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name.c_str(), log_signal(bit), db.module->name.c_str(), proc->name.c_str());
log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name, log_signal(bit), db.module->name, proc->name);
}
db.initvals.remove_init(bit);
}

2
passes/proc/proc_init.cc
View file

@ -31,7 +31,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
for (auto &sync : proc->syncs)
if (sync->type == RTLIL::SyncType::STi)
{
log("Found init rule in `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
log("Found init rule in `%s.%s'.\n", mod->name, proc->name);
for (auto &action : sync->actions)
{

2
passes/proc/proc_mux.cc
View file

@ -412,7 +412,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode)
{
log("Creating decoders for process `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
log("Creating decoders for process `%s.%s'.\n", mod->name, proc->name);
SigSnippets sigsnip;
sigsnip.insert(&proc->root_case);

32
passes/sat/eval.cc
View file

@ -87,7 +87,7 @@ struct BruteForceEquivChecker
BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) :
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name, mod2->name);
for (auto w : mod1->wires())
{
if (w->port_id == 0)
@ -264,7 +264,7 @@ struct VlogHammerReporter
if (!ce.eval(sig))
log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str());
log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string());
}
}
@ -280,7 +280,7 @@ struct VlogHammerReporter
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str());
log("++VAL++ %d %s %s #\n", idx, module_name, sig.as_const().as_string());
if (module_name == "rtl") {
rtl_sig = sig;
@ -294,7 +294,7 @@ struct VlogHammerReporter
sig[i] = RTLIL::State::Sx;
}
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list, sig.as_const().as_string(), module_name);
}
log("++RPT++ ----\n");
@ -307,8 +307,8 @@ struct VlogHammerReporter
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
if (design->module(esc_name) == nullptr)
log_error("Can't find module %s in current design!\n", name.c_str());
log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
log_error("Can't find module %s in current design!\n", name);
log("Using module %s (%s).\n", esc_name, name);
modules.push_back(design->module(esc_name));
module_names.push_back(name);
}
@ -319,15 +319,15 @@ struct VlogHammerReporter
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
if (mod->wire(esc_name) == nullptr)
log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name));
log_error("Can't find input %s in module %s!\n", name, log_id(mod->name));
RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name));
log_error("Wire %s in module %s is not an input!\n", name, log_id(mod->name));
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name.c_str());
log_error("Port %s has different sizes in the different modules!\n", name);
width = port->width;
}
log("Using input port %s with width %d.\n", esc_name.c_str(), width);
log("Using input port %s with width %d.\n", esc_name, width);
inputs.push_back(esc_name);
input_widths.push_back(width);
total_input_width += width;
@ -341,9 +341,9 @@ struct VlogHammerReporter
pattern = pattern.substr(1);
}
if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const())
log_error("Failed to parse pattern %s!\n", pattern.c_str());
log_error("Failed to parse pattern %s!\n", pattern);
if (sig.size() < total_input_width)
log_error("Pattern %s is to short!\n", pattern.c_str());
log_error("Pattern %s is to short!\n", pattern);
patterns.push_back(sig.as_const());
if (invert_pattern) {
for (auto &bit : patterns.back().bits())
@ -352,7 +352,7 @@ struct VlogHammerReporter
else if (bit == RTLIL::State::S1)
bit = RTLIL::State::S0;
}
log("Using pattern %s.\n", patterns.back().as_string().c_str());
log("Using pattern %s.\n", patterns.back().as_string());
}
}
};
@ -415,9 +415,9 @@ struct EvalPass : public Pass {
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
if (design->module(mod1_name) == nullptr)
log_error("Can't find module `%s'!\n", mod1_name.c_str());
log_error("Can't find module `%s'!\n", mod1_name);
if (design->module(mod2_name) == nullptr)
log_error("Can't find module `%s'!\n", mod2_name.c_str());
log_error("Can't find module `%s'!\n", mod2_name);
BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivalent!\n");
@ -574,7 +574,7 @@ struct EvalPass : public Pass {
for (auto &row : tab) {
for (size_t i = 0; i < row.size(); i++) {
int k = int(i) < tab_sep_colidx ? tab_sep_colidx - i - 1 : i;
log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k].c_str());
log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k]);
}
log("\n");
if (first) {

10
passes/sat/fminit.cc
View file

@ -109,7 +109,7 @@ struct FminitPass : public Pass {
SigSpec clksig;
if (!clocksignal.empty()) {
if (!SigSpec::parse(clksig, module, clocksignal))
log_error("Error parsing expression '%s'.\n", clocksignal.c_str());
log_error("Error parsing expression '%s'.\n", clocksignal);
}
for (auto &it : setdata)
@ -117,10 +117,10 @@ struct FminitPass : public Pass {
SigSpec lhs, rhs;
if (!SigSpec::parse(lhs, module, it.first))
log_error("Error parsing expression '%s'.\n", it.first.c_str());
log_error("Error parsing expression '%s'.\n", it.first);
if (!SigSpec::parse_rhs(lhs, rhs, module, it.second))
log_error("Error parsing expression '%s'.\n", it.second.c_str());
log_error("Error parsing expression '%s'.\n", it.second);
SigSpec final_lhs, final_rhs;
@ -144,7 +144,7 @@ struct FminitPass : public Pass {
SigSpec lhs, rhs;
if (!SigSpec::parse(lhs, module, it.first))
log_error("Error parsing expression '%s'.\n", it.first.c_str());
log_error("Error parsing expression '%s'.\n", it.first);
for (int i = 0; i < GetSize(it.second); i++)
{
@ -183,7 +183,7 @@ struct FminitPass : public Pass {
SigSpec final_lhs, final_rhs;
if (!SigSpec::parse_rhs(lhs, rhs, module, it.second[i]))
log_error("Error parsing expression '%s'.\n", it.second[i].c_str());
log_error("Error parsing expression '%s'.\n", it.second[i]);
for (int i = 0; i < GetSize(rhs); i++)
if (rhs[i] != State::Sz) {

4
passes/sat/freduce.cc
View file

@ -247,7 +247,7 @@ struct PerformReduction
string loop_signals;
for (auto loop_bit : recursion_guard)
loop_signals += string(" ") + log_signal(loop_bit);
log_error("Found logic loop:%s\n", loop_signals.c_str());
log_error("Found logic loop:%s\n", loop_signals);
}
recursion_guard.insert(out);
@ -596,7 +596,7 @@ struct FreduceWorker
void dump()
{
std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter);
log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename.c_str());
log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename);
Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : ""));
}

8
passes/sat/mutate.cc
View file

@ -539,7 +539,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
std::ofstream sout;
sout.open(srcsfile, std::ios::out | std::ios::trunc);
if (!sout.is_open())
log_error("Could not open file \"%s\" with write access.\n", srcsfile.c_str());
log_error("Could not open file \"%s\" with write access.\n", srcsfile);
sources.sort();
for (auto &s : sources)
sout << s << std::endl;
@ -550,7 +550,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (!filename.empty()) {
fout.open(filename, std::ios::out | std::ios::trunc);
if (!fout.is_open())
log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
log_error("Could not open file \"%s\" with write access.\n", filename);
}
int ctrl_value = opts.ctrl_value;
@ -561,7 +561,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += " -mode none";
if (filename.empty())
log("%s\n", str.c_str());
log("%s\n", str);
else
fout << str << std::endl;
}
@ -588,7 +588,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto &s : entry.src)
str += stringf(" -src %s", s);
if (filename.empty())
log("%s\n", str.c_str());
log("%s\n", str);
else
fout << str << std::endl;
}

22
passes/sat/qbfsat.cc
View file

@ -122,7 +122,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
for (auto &it : hole_assignments) {
RTLIL::SigSpec lhs(it.first);
RTLIL::SigSpec rhs(it.second);
log("Specializing %s from file with %s = %d.\n", module->name.c_str(), log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0);
log("Specializing %s from file with %s = %d.\n", module->name, log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0);
module->connect(lhs, rhs);
}
}
@ -151,7 +151,7 @@ void specialize(RTLIL::Module *module, const QbfSolutionType &sol, bool quiet =
RTLIL::SigSpec lhs(hole_sigbit.wire, hole_sigbit.offset, 1);
RTLIL::State hole_bit_val = hole_value[bit_idx] == '1'? RTLIL::State::S1 : RTLIL::State::S0;
if (!quiet)
log("Specializing %s with %s = %d.\n", module->name.c_str(), log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1)
log("Specializing %s with %s = %d.\n", module->name, log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1)
;
module->connect(lhs, hole_bit_val);
}
@ -168,7 +168,7 @@ void allconstify_inputs(RTLIL::Module *module, const pool<std::string> &input_wi
allconst->setPort(ID::Y, input);
allconst->set_src_attribute(input->get_src_attribute());
input->port_input = false;
log("Replaced input %s with $allconst cell.\n", n.c_str());
log("Replaced input %s with $allconst cell.\n", n);
}
module->fixup_ports();
}
@ -184,7 +184,7 @@ void assume_miter_outputs(RTLIL::Module *module, bool assume_neg) {
else {
log("Adding $assume cell for output(s): ");
for (auto w : wires_to_assume)
log("\"%s\" ", w->name.c_str());
log("\"%s\" ", w->name);
log("\n");
}
@ -236,10 +236,10 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt,
log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str());
else
if (opt.show_smtbmc && !quiet)
log("smtbmc output: %s", line.c_str());
log("smtbmc output: %s", line);
};
log_header(mod->design, "Solving QBF-SAT problem.\n");
if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd.c_str());
if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd);
int64_t begin = PerformanceTimer::query();
run_command(smtbmc_cmd, process_line);
int64_t end = PerformanceTimer::query();
@ -303,7 +303,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
log_assert(wire_to_optimize_name != "");
log_assert(module->wire(wire_to_optimize_name) != nullptr);
log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name.c_str());
log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name);
//If maximizing, grow until we get a failure. Then bisect success and failure.
while (failure == 0 || difference(success, failure) > 1) {
@ -316,7 +316,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
: module->Le(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false);
module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1));
log("Trying to solve with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), cur_thresh);
log("Trying to solve with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), cur_thresh);
}
ret = call_qbf_solver(module, opt, tempdir_name, false, iter_num);
@ -337,7 +337,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
log_assert(value.is_fully_const());
success = value.as_const().as_int();
best_soln = ret;
log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name.c_str(), success);
log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name, success);
Pass::call(design, "design -pop");
module = design->module(module_name);
@ -355,7 +355,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
break;
}
else
log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), failure);
log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), failure);
}
iter_num++;
@ -367,7 +367,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
cur_thresh = (success + failure) / 2; //bisection
}
if (success != 0 || failure != 0) {
log("Wire %s is %s at %d.\n", wire_to_optimize_name.c_str(), (maximize? "maximized" : "minimized"), success);
log("Wire %s is %s at %d.\n", wire_to_optimize_name, (maximize? "maximized" : "minimized"), success);
ret = best_soln;
}
}

12
passes/sat/sat.cc
View file

@ -652,9 +652,9 @@ struct SatHelper
log(" ");
if (info.width <= 32 && !found_undef)
log("%-*s %11d %9x %*s\n", maxModelName+5, info.description.c_str(), value.as_int(), value.as_int(), maxModelWidth+3, value.as_string().c_str());
log("%-*s %11d %9x %*s\n", maxModelName+5, info.description, value.as_int(), value.as_int(), maxModelWidth+3, value.as_string());
else
log("%-*s %11s %9s %*s\n", maxModelName+5, info.description.c_str(), "--", "--", maxModelWidth+3, value.as_string().c_str());
log("%-*s %11s %9s %*s\n", maxModelName+5, info.description, "--", "--", maxModelWidth+3, value.as_string());
}
if (last_timestep == -2)
@ -668,7 +668,7 @@ struct SatHelper
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno));
log("Dumping SAT model to VCD file %s\n", vcd_file_name.c_str());
log("Dumping SAT model to VCD file %s\n", vcd_file_name);
time_t timestamp;
struct tm* now;
@ -772,7 +772,7 @@ struct SatHelper
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno));
log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name.c_str());
log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name);
int mintime = 1, maxtime = 0, maxwidth = 0;;
dict<string, pair<int, dict<int, Const>>> wavedata;
@ -1530,7 +1530,7 @@ struct SatPass : public Pass {
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno));
log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str());
log("Dumping CNF to file `%s'.\n", cnf_file_name);
cnf_file_name.clear();
inductstep.ez->printDIMACS(f, false);
@ -1634,7 +1634,7 @@ struct SatPass : public Pass {
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno));
log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str());
log("Dumping CNF to file `%s'.\n", cnf_file_name);
cnf_file_name.clear();
sathelper.ez->printDIMACS(f, false);

60
passes/sat/sim.cc
View file

@ -60,10 +60,10 @@ static double stringToTime(std::string str)
long value = strtol(str.c_str(), &endptr, 10);
if (g_units.find(endptr)==g_units.end())
log_error("Cannot parse '%s', bad unit '%s'\n", str.c_str(), endptr);
log_error("Cannot parse '%s', bad unit '%s'\n", str, endptr);
if (value < 0)
log_error("Time value '%s' must be positive\n", str.c_str());
log_error("Time value '%s' must be positive\n", str);
return value * pow(10.0, g_units.at(endptr));
}
@ -430,7 +430,7 @@ struct SimInstance
value.bits().push_back(State::Sz);
if (shared->debug)
log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value));
return value;
}
@ -449,7 +449,7 @@ struct SimInstance
}
if (shared->debug)
log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
log("[%s] set %s: %s\n", hiername(), log_signal(sig), log_signal(value));
return did_something;
}
@ -551,7 +551,7 @@ struct SimInstance
if (has_y) sig_y = cell->getPort(ID::Y);
if (shared->debug)
log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type));
// Simple (A -> Y) and (A,B -> Y) cells
if (has_a && !has_c && !has_d && !has_s && has_y) {
@ -793,14 +793,14 @@ struct SimInstance
static void log_source(RTLIL::AttrObject *src)
{
for (auto src : src->get_strpool_attribute(ID::src))
log(" %s\n", src.c_str());
log(" %s\n", src);
}
void log_cell_w_hierarchy(std::string opening_verbiage, RTLIL::Cell *cell)
{
log_assert(cell->module == module);
bool has_src = cell->has_attribute(ID::src);
log("%s %s%s\n", opening_verbiage.c_str(),
log("%s %s%s\n", opening_verbiage,
log_id(cell), has_src ? " at" : "");
log_source(cell);
@ -894,7 +894,7 @@ struct SimInstance
}
std::string rendered = print.fmt.render();
log("%s", rendered.c_str());
log("%s", rendered);
shared->display_output.emplace_back(shared->step, this, cell, rendered);
}
}
@ -921,15 +921,15 @@ struct SimInstance
}
if (cell->type == ID($cover) && en == State::S1 && a == State::S1)
log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str());
log("Cover %s.%s (%s) reached.\n", hiername(), log_id(cell), label);
if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
log("Assumption %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
if (cell->type == ID($assert) && en == State::S1 && a != State::S1) {
log_cell_w_hierarchy("Failed assertion", cell);
if (shared->serious_asserts)
log_error("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
else
log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
}
@ -952,7 +952,7 @@ struct SimInstance
{
if (!ff_database.empty() || !mem_database.empty()) {
if (wbmods.count(module))
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module));
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername(), log_id(module));
wbmods.insert(module);
}
@ -1192,7 +1192,7 @@ struct SimInstance
}
}
if (!found)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)).c_str());
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)));
}
}
}
@ -1478,7 +1478,7 @@ struct SimWorker : SimShared
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
fst_clock.push_back(id);
}
for (auto portname : clockn)
@ -1490,7 +1490,7 @@ struct SimWorker : SimShared
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
fst_clock.push_back(id);
}
@ -1500,7 +1500,7 @@ struct SimWorker : SimShared
if (wire->port_input) {
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)));
top->fst_inputs[wire] = id;
}
}
@ -1623,9 +1623,9 @@ struct SimWorker : SimShared
else if (type == "latch")
mem_latches[variable] = { memid, offset };
else
log_error("Map file addressing cell %s as type %s\n", symbol.c_str(), type.c_str());
log_error("Map file addressing cell %s as type %s\n", symbol, type);
} else {
log_error("Cell %s in map file is not memory cell\n", symbol.c_str());
log_error("Cell %s in map file is not memory cell\n", symbol);
}
} else {
if (index < w->start_offset || index > w->start_offset + w->width)
@ -1645,7 +1645,7 @@ struct SimWorker : SimShared
std::ifstream f;
f.open(sim_filename.c_str());
if (f.fail() || GetSize(sim_filename) == 0)
log_error("Can not open file `%s`\n", sim_filename.c_str());
log_error("Can not open file `%s`\n", sim_filename);
int state = 0;
std::string status;
@ -1729,7 +1729,7 @@ struct SimWorker : SimShared
if (pos==std::string::npos) {
pos = name.find_first_of("#");
if (pos==std::string::npos)
log_error("Line does not contain proper signal name `%s`\n", name.c_str());
log_error("Line does not contain proper signal name `%s`\n", name);
}
return name.substr(0, pos);
}
@ -1744,7 +1744,7 @@ struct SimWorker : SimShared
std::ifstream f;
f.open(sim_filename.c_str());
if (f.fail() || GetSize(sim_filename) == 0)
log_error("Can not open file `%s`\n", sim_filename.c_str());
log_error("Can not open file `%s`\n", sim_filename);
int state = 0;
int cycle = 0;
@ -1874,7 +1874,7 @@ struct SimWorker : SimShared
if (item.wire != nullptr) {
if (paths.count(path)) {
if (debug)
log("witness hierarchy: found wire %s\n", path.str().c_str());
log("witness hierarchy: found wire %s\n", path.str());
bool inserted = hierarchy.paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second;
if (!inserted)
log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str());
@ -1883,7 +1883,7 @@ struct SimWorker : SimShared
auto it = mem_paths.find(path);
if (it != mem_paths.end()) {
if (debug)
log("witness hierarchy: found mem %s\n", path.str().c_str());
log("witness hierarchy: found mem %s\n", path.str());
IdPath word_path = path;
word_path.emplace_back();
for (auto addr_part : it->second) {
@ -1951,7 +1951,7 @@ struct SimWorker : SimShared
Const value = yw.get_bits(t, signal.bits_offset, signal.width);
if (debug)
log("yw: set %s to %s\n", signal.path.str().c_str(), log_const(value));
log("yw: set %s to %s\n", signal.path.str(), log_const(value));
if (found_path.wire != nullptr) {
found_path.instance->set_state_parent_drivers(
@ -2052,7 +2052,7 @@ struct SimWorker : SimShared
PrettyJson json;
if (!json.write_to_file(summary_filename))
log_error("Can't open file `%s' for writing: %s\n", summary_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", summary_filename, strerror(errno));
json.begin_object();
json.entry("version", "Yosys sim summary");
@ -2134,7 +2134,7 @@ struct SimWorker : SimShared
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2147,7 +2147,7 @@ struct SimWorker : SimShared
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2159,7 +2159,7 @@ struct SimWorker : SimShared
for (auto wire : topmod->wires()) {
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0 && (wire->port_input || wire->port_output))
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)));
if (wire->port_input)
if (clocks.find(wire)==clocks.end())
inputs[wire] = id;
@ -2236,7 +2236,7 @@ struct SimWorker : SimShared
f << "\n";
f << "\tinteger i;\n";
uint64_t prev_time = startCount;
log("Writing data to `%s`\n", (tb_filename+".txt").c_str());
log("Writing data to `%s`\n", (tb_filename+".txt"));
std::ofstream data_file(tb_filename+".txt");
std::stringstream initstate;
unsigned int end_cycle = cycles_set ? numcycles*2 : INT_MAX;
@ -2292,7 +2292,7 @@ struct SimWorker : SimShared
f << "\tend\n";
f << "endmodule\n";
log("Writing testbench to `%s`\n", (tb_filename+".v").c_str());
log("Writing testbench to `%s`\n", (tb_filename+".v"));
std::ofstream tb_file(tb_filename+".v");
tb_file << f.str();

2
passes/sat/synthprop.cc
View file

@ -170,7 +170,7 @@ void SynthPropWorker::run()
std::ofstream fout;
fout.open(map_file, std::ios::out | std::ios::trunc);
if (!fout.is_open())
log_error("Could not open file \"%s\" with write access.\n", map_file.c_str());
log_error("Could not open file \"%s\" with write access.\n", map_file);
for (auto name : tracing_data[module].names) {
fout << name << std::endl;

42
passes/techmap/abc.cc
View file

@ -751,7 +751,7 @@ struct abc_output_filter
return;
}
if (ch == '\n') {
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir));
got_cr = false, linebuf.clear();
return;
}
@ -936,7 +936,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
std::string buffer = stringf("%s/abc.script", tempdir_name);
FILE *f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
fprintf(f, "%s\n", abc_script.c_str());
fclose(f);
@ -991,7 +991,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
buffer = stringf("%s/input.blif", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
fprintf(f, ".model netlist\n");
@ -1118,7 +1118,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
buffer = stringf("%s/stdcells.genlib", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
@ -1163,14 +1163,14 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
buffer = stringf("%s/lutdefs.txt", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
for (int i = 0; i < GetSize(config.lut_costs); i++)
fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i));
fclose(f);
}
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name);
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir).c_str());
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir));
#ifndef YOSYS_LINK_ABC
abc_output_filter filt(*this, tempdir_name, config.show_tempdir);
@ -1220,7 +1220,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
temp_stdouterr_r.close();
#endif
if (ret != 0) {
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
return;
}
did_run_abc = true;
@ -1239,7 +1239,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
std::ifstream ifs;
ifs.open(buffer);
if (ifs.fail())
log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
log_error("Can't open ABC output file `%s'.\n", buffer);
bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty();
RTLIL::Design *mapped_design = new RTLIL::Design;
@ -1490,7 +1490,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
cell_stats.sort();
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second);
int in_wires = 0, out_wires = 0;
for (auto &si : signal_list)
if (si.is_port) {
@ -1582,7 +1582,7 @@ struct AbcPass : public Pass {
#ifdef ABCEXTERNAL
log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
#else
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str());
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix());
#endif
log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
log("\n");
@ -1597,41 +1597,41 @@ struct AbcPass : public Pass {
log(" if no -script parameter is given, the following scripts are used:\n");
log("\n");
log(" for -liberty/-genlib without -constr:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB));
log("\n");
log(" for -liberty/-genlib with -constr:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR));
log("\n");
log(" for -lut/-luts (only one LUT size):\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}"));
log("\n");
log(" for -lut/-luts (different LUT sizes):\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT));
log("\n");
log(" for -sop:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP));
log("\n");
log(" otherwise:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL));
log("\n");
log(" -fast\n");
log(" use different default scripts that are slightly faster (at the cost\n");
log(" of output quality):\n");
log("\n");
log(" for -liberty/-genlib without -constr:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB));
log("\n");
log(" for -liberty/-genlib with -constr:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR));
log("\n");
log(" for -lut/-luts:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT));
log("\n");
log(" for -sop:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP));
log("\n");
log(" otherwise:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL));
log("\n");
log(" -liberty <file>\n");
log(" generate netlists for the specified cell library (using the liberty\n");

6
passes/techmap/abc9.cc
View file

@ -106,7 +106,7 @@ struct Abc9Pass : public ScriptPass
#ifdef ABCEXTERNAL
log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
#else
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str());
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix());
#endif
log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
log("\n");
@ -119,12 +119,12 @@ struct Abc9Pass : public ScriptPass
log(" replaced with blanks before the string is passed to ABC.\n");
log("\n");
log(" if no -script parameter is given, the following scripts are used:\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str());
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)));
log("\n");
log(" -fast\n");
log(" use different default scripts that are slightly faster (at the cost\n");
log(" of output quality):\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)));
log("\n");
log(" -D <picoseconds>\n");
log(" set delay target. the string {D} in the default scripts above is\n");

14
passes/techmap/abc9_exe.cc
View file

@ -140,7 +140,7 @@ struct abc9_output_filter
return;
}
if (ch == '\n') {
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir));
got_cr = false, linebuf.clear();
return;
}
@ -271,14 +271,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
buffer = stringf("%s/lutdefs.txt", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == NULL)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
for (int i = 0; i < GetSize(lut_costs); i++)
fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
fclose(f);
}
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file, tempdir_name);
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir));
#ifndef YOSYS_LINK_ABC
abc9_output_filter filt(tempdir_name, show_tempdir);
@ -331,7 +331,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
if (check_file_exists(stringf("%s/output.aig", tempdir_name)))
log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
else
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
}
}
@ -352,7 +352,7 @@ struct Abc9ExePass : public Pass {
#ifdef ABCEXTERNAL
log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
#else
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str());
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix());
#endif
log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
log("\n");
@ -365,12 +365,12 @@ struct Abc9ExePass : public Pass {
log(" replaced with blanks before the string is passed to ABC.\n");
log("\n");
log(" if no -script parameter is given, the following scripts are used:\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str());
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)));
log("\n");
log(" -fast\n");
log(" use different default scripts that are slightly faster (at the cost\n");
log(" of output quality):\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)));
log("\n");
log(" -constr <file>\n");
log(" pass this file with timing constraints to ABC.\n");

4
passes/techmap/abc9_ops.cc
View file

@ -787,7 +787,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto cell_name : it) {
auto cell = module->cell(cell_name);
log_assert(cell);
log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute());
}
}
}
@ -1444,7 +1444,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
}
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second);
int in_wires = 0, out_wires = 0;
// Stitch in mapped_mod's inputs/outputs into module

4
passes/techmap/attrmap.cc
View file

@ -130,14 +130,14 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
goto delete_this_attr;
if (new_attr != attr)
log("Changed attribute on %s: %s=%s -> %s=%s\n", objname.c_str(),
log("Changed attribute on %s: %s=%s -> %s=%s\n", objname,
log_id(attr.first), log_const(attr.second), log_id(new_attr.first), log_const(new_attr.second));
new_attributes[new_attr.first] = new_attr.second;
if (0)
delete_this_attr:
log("Removed attribute on %s: %s=%s\n", objname.c_str(), log_id(attr.first), log_const(attr.second));
log("Removed attribute on %s: %s=%s\n", objname, log_id(attr.first), log_const(attr.second));
}
attributes.swap(new_attributes);

4
passes/techmap/clkbufmap.cc
View file

@ -257,14 +257,14 @@ struct ClkbufmapPass : public Pass {
RTLIL::Cell *cell = nullptr;
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i);
log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i);
cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_ID);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i);
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);

6
passes/techmap/clockgate.cc
View file

@ -81,7 +81,7 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
} else if (icg_kind == "latch_negedge" || starts_with("latch_negedge_")) {
clk_pol = false;
} else {
log("Ignoring ICG primitive %s of kind '%s'\n", cell_name.c_str(), icg_kind.c_str());
log("Ignoring ICG primitive %s of kind '%s'\n", cell_name, icg_kind);
continue;
}
@ -176,11 +176,11 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
std::optional<ClockGateCell> pos;
std::optional<ClockGateCell> neg;
if (best_pos) {
log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str());
log("Selected rising edge ICG %s from Liberty file\n", best_pos->name);
pos.emplace(*best_pos);
}
if (best_neg) {
log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str());
log("Selected falling edge ICG %s from Liberty file\n", best_neg->name);
neg.emplace(*best_neg);
}
return std::make_pair(pos, neg);

6
passes/techmap/dfflegalize.cc
View file

@ -1111,7 +1111,7 @@ struct DffLegalizePass : public Pass {
pol_r = celltype[13];
} else {
unrecognized:
log_error("unrecognized cell type %s.\n", celltype.c_str());
log_error("unrecognized cell type %s.\n", celltype);
}
int mask = 0;
int match = 0;
@ -1140,12 +1140,12 @@ unrecognized:
initmask = 0x555;
} else if (inittype == "r") {
if (srval == 0)
log_error("init type r not valid for cell type %s.\n", celltype.c_str());
log_error("init type r not valid for cell type %s.\n", celltype);
initmask = 0x537;
} else if (inittype == "01") {
initmask = 0x777;
} else {
log_error("unrecognized init type %s for cell type %s.\n", inittype.c_str(), celltype.c_str());
log_error("unrecognized init type %s for cell type %s.\n", inittype, celltype);
}
if (srval == '0') {
initmask &= 0x0ff;

10
passes/techmap/dfflibmap.cc
View file

@ -36,9 +36,9 @@ static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
static void logmap(IdString dff)
{
if (cell_mappings.count(dff) == 0) {
log(" unmapped dff cell: %s\n", dff.c_str());
log(" unmapped dff cell: %s\n", dff);
} else {
log(" %s %s (", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str());
log(" %s %s (", cell_mappings[dff].cell_name, dff.substr(1));
bool first = true;
for (auto &port : cell_mappings[dff].ports) {
char arg[3] = { port.second, 0, 0 };
@ -46,7 +46,7 @@ static void logmap(IdString dff)
arg[1] = arg[0] - ('a' - 'A'), arg[0] = '~';
else
arg[1] = arg[0], arg[0] = ' ';
log("%s.%s(%s)", first ? "" : ", ", port.first.c_str(), arg);
log("%s.%s(%s)", first ? "" : ", ", port.first, arg);
first = false;
}
log(");\n");
@ -488,7 +488,7 @@ static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_ty
static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
{
log("Mapping DFF cells in module `%s':\n", module->name.c_str());
log("Mapping DFF cells in module `%s':\n", module->name);
dict<SigBit, pool<Cell*>> notmap;
SigMap sigmap(module);
@ -690,7 +690,7 @@ struct DfflibmapPass : public Pass {
dfflegalize_cmd += stringf(" -cell %s 01", it.first);
dfflegalize_cmd += " t:$_DFF* t:$_SDFF*";
if (info_mode) {
log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str());
log("dfflegalize command line: %s\n", dfflegalize_cmd);
} else {
Pass::call(design, dfflegalize_cmd);
}

16
passes/techmap/extract.cc
View file

@ -627,7 +627,7 @@ struct ExtractPass : public Pass {
for (auto module : map->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "needle_" + RTLIL::unescape_id(module->name);
log("Creating needle graph %s.\n", graph_name.c_str());
log("Creating needle graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports)) {
solver.addGraph(graph_name, mod_graph);
needle_map[graph_name] = module;
@ -638,7 +638,7 @@ struct ExtractPass : public Pass {
for (auto module : design->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "haystack_" + RTLIL::unescape_id(module->name);
log("Creating haystack graph %s.\n", graph_name.c_str());
log("Creating haystack graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) {
solver.addGraph(graph_name, mod_graph);
haystack_map[graph_name] = module;
@ -654,7 +654,7 @@ struct ExtractPass : public Pass {
for (auto needle : needle_list)
for (auto &haystack_it : haystack_map) {
log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)).c_str(), haystack_it.first.c_str());
log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)), haystack_it.first);
solver.solve(results, "needle_" + RTLIL::unescape_id(needle->name), haystack_it.first, false);
}
log("Found %d matches.\n", GetSize(results));
@ -665,11 +665,11 @@ struct ExtractPass : public Pass {
for (int i = 0; i < int(results.size()); i++) {
auto &result = results[i];
log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId.c_str(), result.haystackGraphId.c_str());
log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId, result.haystackGraphId);
for (const auto &it : result.mappings) {
log(" %s -> %s", it.first.c_str(), it.second.haystackNodeId.c_str());
log(" %s -> %s", it.first, it.second.haystackNodeId);
for (const auto & it2 : it.second.portMapping)
log(" %s:%s", it2.first.c_str(), it2.second.c_str());
log(" %s:%s", it2.first, it2.second);
log("\n");
}
RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
@ -693,7 +693,7 @@ struct ExtractPass : public Pass {
log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
log(" primary match in %s:", log_id(haystack_map.at(result.graphId)->name));
for (auto &node : result.nodes)
log(" %s", RTLIL::unescape_id(node.nodeId).c_str());
log(" %s", RTLIL::unescape_id(node.nodeId));
log("\n");
for (auto &it : result.matchesPerGraph)
log(" matches in %s: %d\n", log_id(haystack_map.at(it.first)->name), it.second);
@ -744,7 +744,7 @@ struct ExtractPass : public Pass {
rewrite_filename(mine_outfile);
f.open(mine_outfile.c_str(), std::ofstream::trunc);
if (f.fail())
log_error("Can't open output file `%s'.\n", mine_outfile.c_str());
log_error("Can't open output file `%s'.\n", mine_outfile);
Backend::backend_call(map, &f, mine_outfile, "rtlil");
f.close();
}

6
passes/techmap/extract_counter.cc
View file

@ -847,7 +847,7 @@ struct ExtractCounterPass : public Pass {
else if (arg == "no")
settings.allow_arst = false;
else
log_error("Invalid -allow_arst value \"%s\"\n", arg.c_str());
log_error("Invalid -allow_arst value \"%s\"\n", arg);
continue;
}
@ -861,7 +861,7 @@ struct ExtractCounterPass : public Pass {
else if (arg == "both")
settings.allowed_dirs = 2;
else
log_error("Invalid -dir value \"%s\"\n", arg.c_str());
log_error("Invalid -dir value \"%s\"\n", arg);
continue;
}
}
@ -893,7 +893,7 @@ struct ExtractCounterPass : public Pass {
for(auto cpair : cells_to_rename)
{
//log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second.c_str());
//log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second);
module->rename(cpair.first, cpair.second);
}
}

4
passes/techmap/extract_reduce.cc
View file

@ -133,7 +133,7 @@ struct ExtractReducePass : public Pass
else
continue;
log("Working on cell %s...\n", cell->name.c_str());
log("Working on cell %s...\n", cell->name);
// If looking for a single chain, follow linearly to the sink
pool<Cell*> sinks;
@ -220,7 +220,7 @@ struct ExtractReducePass : public Pass
//We have our list, go act on it
for(auto head_cell : sinks)
{
log(" Head cell is %s\n", head_cell->name.c_str());
log(" Head cell is %s\n", head_cell->name);
//Avoid duplication if we already were covered
if(consumed_cells.count(head_cell))

2
passes/techmap/extractinv.cc
View file

@ -111,7 +111,7 @@ struct ExtractinvPass : public Pass {
RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, log_id(module), log_id(cell->type), log_id(port.first), i);
sig[i] = SigBit(iwire, i);
}
cell->setPort(port.first, sig);

2
passes/techmap/flowmap.cc
View file

@ -598,7 +598,7 @@ struct FlowmapWorker
continue;
if (!cell->known())
log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell));
log_error("Cell %s (%s.%s) is unknown.\n", cell->type, log_id(module), log_id(cell));
pool<RTLIL::SigBit> fanout;
for (auto conn : cell->connections())

6
passes/techmap/iopadmap.cc
View file

@ -324,7 +324,7 @@ struct IopadmapPass : public Pass {
if (wire->port_input)
{
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
@ -348,7 +348,7 @@ struct IopadmapPass : public Pass {
if (!tinoutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad));
} else {
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
@ -421,7 +421,7 @@ struct IopadmapPass : public Pass {
continue;
}
log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype);
if (flag_bits)
{

4
passes/techmap/libcache.cc
View file

@ -117,9 +117,9 @@
if (list) {
log("Caching is %s by default.\n", LibertyAstCache::instance.cache_by_default ? "enabled" : "disabled");
for (auto const &entry : LibertyAstCache::instance.cache_path)
log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first.c_str());
log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first);
for (auto const &entry : LibertyAstCache::instance.cached)
log("Data for `%s' is currently cached.\n", entry.first.c_str());
log("Data for `%s' is currently cached.\n", entry.first);
} else if (enable || disable) {
if (all) {
LibertyAstCache::instance.cache_by_default = enable;

6
passes/techmap/libparse.cc
View file

@ -42,7 +42,7 @@ std::shared_ptr<const LibertyAst> LibertyAstCache::cached_ast(const std::string
if (it == cached.end())
return nullptr;
if (verbose)
log("Using cached data for liberty file `%s'\n", fname.c_str());
log("Using cached data for liberty file `%s'\n", fname);
return it->second;
}
@ -53,7 +53,7 @@ void LibertyAstCache::parsed_ast(const std::string &fname, const std::shared_ptr
if (!should_cache)
return;
if (verbose)
log("Caching data for liberty file `%s'\n", fname.c_str());
log("Caching data for liberty file `%s'\n", fname);
cached.emplace(fname, ast);
}
@ -671,7 +671,7 @@ void LibertyParser::error(const std::string &str) const
std::stringstream ss;
ss << "Syntax error in liberty file on line " << line << ".\n";
ss << " " << str << "\n";
log_error("%s", ss.str().c_str());
log_error("%s", ss.str());
}
#else

2
passes/techmap/libparse.h
View file

@ -204,7 +204,7 @@ namespace Yosys
}
ast = shared_ast.get();
if (!ast) {
log_error("No entries found in liberty file `%s'.\n", fname.c_str());
log_error("No entries found in liberty file `%s'.\n", fname);
}
}
#endif

10
passes/techmap/techmap.cc
View file

@ -247,7 +247,7 @@ struct TechmapWorker
portname = positional_ports.at(portname);
if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
if (portname.begins_with("$"))
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname, cell->name, tpl->name);
continue;
}
@ -562,7 +562,7 @@ struct TechmapWorker
if (extmapper_name == "wrap") {
std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
log("Running \"%s\" on wrapper %s.\n", cmd_string, log_id(extmapper_module));
mkdebug.on();
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
log_continue = true;
@ -580,7 +580,7 @@ struct TechmapWorker
auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg.c_str());
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
}
@ -589,7 +589,7 @@ struct TechmapWorker
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, log_id(cell->type));
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg.c_str());
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
@ -951,7 +951,7 @@ struct TechmapWorker
auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg.c_str());
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
techmap_module_worker(design, module, cell, tpl);

2
passes/tests/raise_error.cc
View file

@ -85,7 +85,7 @@ struct RaiseErrorPass : public Pass {
if (use_stderr) {
std::cerr << err_msg << std::endl;
} else {
log_error("%s\n", err_msg.c_str());
log_error("%s\n", err_msg);
}
}

2
passes/tests/test_autotb.cc
View file

@ -109,7 +109,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
continue;
int count_ports = 0;
log("Generating test bench for module `%s'.\n", mod->name.c_str());
log("Generating test bench for module `%s'.\n", mod->name);
for (auto wire : mod->wires()) {
if (wire->port_output) {
count_ports++;

2
passes/tests/test_cell.cc
View file

@ -722,7 +722,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
}
if (verbose)
log("EVAL: %s\n", out_val.as_string().c_str());
log("EVAL: %s\n", out_val.as_string());
if (!nosat)
{