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Merge pull request #22 from alaindargelas/fix_runtime_write_verilog

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Akash Levy 2024-11-16 13:29:04 -08:00 • committed by GitHub
commit dd7ad14096
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1 changed files with 22 additions and 13 deletions
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27
backends/verilog/verilog_backend.cc
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@ -2347,20 +2347,29 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
}
dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true);
f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
bool keep_running = true;
f << stringf("%s"
"module %s(",
indent.c_str(), id(module->name, false).c_str());
int cnt = 0;
for (int port_id = 1; keep_running; port_id++) {
keep_running = false;
int max_port_id = 0;
for (auto wire : module->wires()) {
if (wire->port_id == port_id) {
max_port_id = std::max(wire->port_id, max_port_id);
}
std::vector<Wire *> wires(max_port_id + 1, nullptr);
for (auto wire : module->wires()) {
wires[wire->port_id] = wire;
}
for (int port_id = 1; port_id < max_port_id; port_id++) {
Wire *wire = wires[port_id];
if (wire) {
if (port_id != 1)
f << stringf(", ");
f << stringf("%s", id(wire->name).c_str());
keep_running = true;
if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
continue;
}
if (cnt == 20) {
f << stringf("\n");
cnt = 0;
} else
cnt++;
}
}
f << stringf(");\n");