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blackbox: Include whiteboxed modules

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-03-17 12:06:09 +00:00
parent 937392ad33
commit dd6d34f461
4 changed files with 19 additions and 4 deletions
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14
tests/various/blackbox_wb.ys Normal file
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read_verilog <<EOT
(* whitebox *)
module box(input a, output q);
assign q = ~a;
endmodule
module top(input a, output q);
box box_i(.a(a), .q(q));
endmodule
EOT
select -assert-count 1 =box/t:$not
blackbox =box
select -assert-count 0 =A:whitebox
select -assert-count 0 =box/t:$not