mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

blackbox: Include whiteboxed modules

Browse source 
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-03-17 12:06:09 +00:00
parent 937392ad33
commit dd6d34f461
4 changed files with 19 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
kernel/rtlil.cc
View file

@ -808,12 +808,12 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
return result;
}
std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const
{
std::vector<RTLIL::Module*> result;
result.reserve(modules_.size());
for (auto &it : modules_)
if (it.second->get_blackbox_attribute())
if (it.second->get_blackbox_attribute(include_wb))
continue;
else if (selected_whole_module(it.first))
result.push_back(it.second);

2
kernel/rtlil.h
View file

@ -1112,7 +1112,7 @@ struct RTLIL::Design
std::vector<RTLIL::Module*> selected_modules() const;
std::vector<RTLIL::Module*> selected_whole_modules() const;
std::vector<RTLIL::Module*> selected_whole_modules_warn() const;
std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
#endif