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Splitnetlist to support const and feed-thru connections

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This commit is contained in:
Alain Dargelas 2024-11-15 15:33:50 -08:00
parent adbf596a7a
commit dd23878416
2 changed files with 29 additions and 11 deletions
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3
Makefile
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@ -241,7 +241,7 @@ LTOFLAGS := $(CLANG_LTO)
ifneq ($(SANITIZER),) ifneq ($(SANITIZER),)
$(info [Clang Sanitizer] $(SANITIZER)) $(info [Clang Sanitizer] $(SANITIZER))
CXXFLAGS += -g -O1 -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=$(SANITIZER) CXXFLAGS += -g -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=$(SANITIZER)
LINKFLAGS += -g -fsanitize=$(SANITIZER) LINKFLAGS += -g -fsanitize=$(SANITIZER)
ifneq ($(findstring address,$(SANITIZER)),) ifneq ($(findstring address,$(SANITIZER)),)
ENABLE_COVER := 0 ENABLE_COVER := 0
@ -749,6 +749,7 @@ OBJS += passes/cmds/activity.o
OBJS += passes/cmds/splitnetlist.o OBJS += passes/cmds/splitnetlist.o
OBJS += passes/cmds/reconstructbusses.o OBJS += passes/cmds/reconstructbusses.o
OBJS += passes/sat/sim.o OBJS += passes/sat/sim.o
OBJS += passes/techmap/bufnorm.o
OBJS += passes/cmds/segv.o OBJS += passes/cmds/segv.o

31
passes/cmds/splitnetlist.cc
View file

@ -153,8 +153,21 @@ struct SplitNetlist : public ScriptPass {
log_error("No design object"); log_error("No design object");
return; return;
} }
bool debug = false;
if (std::getenv("DEBUG_SPLITNETLIST")) {
debug = true;
}
log("Running splitnetlist pass\n"); log("Running splitnetlist pass\n");
log_flush(); log_flush();
// Add buffers for pass-through and connections to constants
// so we can find cells that can be used by submod
Pass::call(design, "bufnorm -buf");
if (debug)
run_pass("write_rtlil post_buf.rtlil");
log("Mapping signals to cells\n"); log("Mapping signals to cells\n");
log_flush(); log_flush();
// Precompute cell output sigspec to cell map // Precompute cell output sigspec to cell map
@ -183,7 +196,7 @@ struct SplitNetlist : public ScriptPass {
for (auto wire : design->top_module()->wires()) { for (auto wire : design->top_module()->wires()) {
if (!wire->port_output) if (!wire->port_output)
continue; continue;
std::string output_port_name = wire->name.c_str(); std::string output_port_name = wire ? wire->name.c_str() : "";
if (output_port_name.empty()) if (output_port_name.empty())
continue; continue;
// We want to truncate the final _<index>_ part of the string // We want to truncate the final _<index>_ part of the string
@ -242,19 +255,23 @@ struct SplitNetlist : public ScriptPass {
log("Creating submods\n"); log("Creating submods\n");
log_flush(); log_flush();
for (CellName_ObjectMap::iterator itr = cellName_ObjectMap.begin(); itr != cellName_ObjectMap.end(); itr++) { for (CellName_ObjectMap::iterator itr = cellName_ObjectMap.begin(); itr != cellName_ObjectMap.end(); itr++) {
// std::cout << "Cluster name: " << itr->first << std::endl; if (debug)
std::cout << "Cluster name: " << itr->first << std::endl;
CellsAndSigs &components = itr->second; CellsAndSigs &components = itr->second;
for (auto cell : components.visitedCells) { for (auto cell : components.visitedCells) {
cell->set_string_attribute(RTLIL::escape_id("submod"), itr->first); cell->set_string_attribute(RTLIL::escape_id("submod"), itr->first);
// std::cout << " CELL: " << cell->name.c_str() << std::endl; if (debug)
std::cout << " CELL: " << cell->name.c_str() << std::endl;
} }
// for (auto sigspec : components.visitedSigSpec) {
// std::cout << " SIG: " << SigName(sigspec) << std::endl;
// }
// std::cout << std::endl;
} }
// Execute the submod command // Execute the submod command
Pass::call(design, "submod -copy"); Pass::call(design, "submod -copy");
// Remove buffers introduced by bufnorm
Pass::call(design, "techmap -D SIMLIB_NOCHECKS -map +/simlib.v t:$buf");
Pass::call(design, "clean");
log("End splitnetlist pass\n"); log("End splitnetlist pass\n");
log_flush(); log_flush();
} }