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Added $meminit support to "memory" command

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This commit is contained in:
Clifford Wolf 2015-02-14 12:55:03 +01:00
parent 913c304fe6
commit dcf2e24240
7 changed files with 99 additions and 49 deletions
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11
passes/memory/memory_map.cc
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@ -80,11 +80,15 @@ struct MemoryMapWorker
{
std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map;
int mem_size = cell->parameters["\\SIZE"].as_int();
int mem_width = cell->parameters["\\WIDTH"].as_int();
int mem_offset = cell->parameters["\\OFFSET"].as_int();
// int mem_offset = cell->parameters["\\OFFSET"].as_int();
int mem_abits = cell->parameters["\\ABITS"].as_int();
SigSpec init_data = cell->getParam("\\INIT");
init_data.extend_u0(mem_size*mem_width, true);
// delete unused memory cell
if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) {
module->remove(cell);
@ -165,7 +169,10 @@ struct MemoryMapWorker
w_out_name = genid(cell->name, "", i, "$q");
RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width);
w_out->start_offset = mem_offset;
SigSpec w_init = init_data.extract(i*mem_width, mem_width);
if (!w_init.is_fully_undef())
w_out->attributes["\\init"] = w_init.as_const();
data_reg_out.push_back(RTLIL::SigSpec(w_out));
c->setPort("\\Q", data_reg_out.back());