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Added cell->known(), cell->input(portname), cell->output(portname)
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2 changed files with 39 additions and 0 deletions
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@ -1140,6 +1140,11 @@ public:
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const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
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const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
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// information about cell ports
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bool known() const;
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bool input(RTLIL::IdString portname) const;
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bool output(RTLIL::IdString portname) const;
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// access cell parameters
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bool hasParam(RTLIL::IdString paramname) const;
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void unsetParam(RTLIL::IdString paramname);
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