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Added cell->known(), cell->input(portname), cell->output(portname)

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This commit is contained in:
Clifford Wolf 2015-02-07 11:40:19 +01:00
parent d5e30978e9
commit dce1fae777
2 changed files with 39 additions and 0 deletions
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34
kernel/rtlil.cc
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@ -19,6 +19,7 @@
#include "kernel/yosys.h"
#include "kernel/macc.h"
#include "kernel/celltypes.h"
#include "frontends/verilog/verilog_frontend.h"
#include "backends/ilang/ilang_backend.h"
@ -1928,6 +1929,39 @@ const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
return connections_;
}
bool RTLIL::Cell::known() const
{
if (yosys_celltypes.cell_known(type))
return true;
if (module && module->design && module->design->module(type))
return true;
return false;
}
bool RTLIL::Cell::input(RTLIL::IdString portname) const
{
if (yosys_celltypes.cell_known(type))
return yosys_celltypes.cell_input(type, portname);
if (module && module->design) {
RTLIL::Module *m = module->design->module(type);
RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
return w && w->port_input;
}
return false;
}
bool RTLIL::Cell::output(RTLIL::IdString portname) const
{
if (yosys_celltypes.cell_known(type))
return yosys_celltypes.cell_output(type, portname);
if (module && module->design) {
RTLIL::Module *m = module->design->module(type);
RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
return w && w->port_output;
}
return false;
}
bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
{
return parameters.count(paramname) != 0;