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quicklogic: ABC9 synthesis

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Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
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4
tests/arch/quicklogic/mux.ys
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@ -30,13 +30,13 @@ proc
equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 4 t:LUT2
select -assert-count 1 t:LUT1
select -assert-count 1 t:LUT3
select -assert-count 2 t:mux4x0
select -assert-count 11 t:inpad
select -assert-count 1 t:outpad
select -assert-none t:LUT2 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
design -load read
hierarchy -top mux16