mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-09 04:31:25 +00:00
Code Activity

quicklogic: ABC9 synthesis

Browse source
This commit is contained in:
Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/arch/quicklogic/logic.ys
View file

@ -7,8 +7,8 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
select -assert-count 2 t:LUT3
select -assert-count 8 t:inpad
select -assert-count 10 t:outpad
select -assert-none t:LUT1 t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D