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quicklogic: ABC9 synthesis

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Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
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5
tests/arch/quicklogic/latches.ys
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@ -32,8 +32,9 @@ proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT3
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4
select -assert-count 5 t:inpad
select -assert-count 1 t:outpad
select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D