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quicklogic: ABC9 synthesis

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Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
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9
tests/arch/quicklogic/fsm.ys
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@ -11,14 +11,13 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 3 t:LUT2
select -assert-count 6 t:LUT3
select -assert-count 7 t:LUT4
select -assert-count 6 t:dffepc
select -assert-count 1 t:LUT2
select -assert-count 9 t:LUT3
select -assert-count 4 t:dffepc
select -assert-count 1 t:logic_0
select -assert-count 1 t:logic_1
select -assert-count 3 t:inpad
select -assert-count 2 t:outpad
select -assert-count 1 t:ckpad
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D