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quicklogic: ABC9 synthesis

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Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
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6
tests/arch/quicklogic/counter.ys
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@ -6,9 +6,9 @@ equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogi
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 5 t:LUT2
select -assert-count 2 t:LUT3
select -assert-count 3 t:LUT4
select -assert-count 3 t:LUT2
select -assert-count 5 t:LUT3
select -assert-count 1 t:LUT4
select -assert-count 8 t:dffepc
select -assert-count 1 t:logic_0
select -assert-count 1 t:logic_1