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quicklogic: ABC9 synthesis

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Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
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6
tests/arch/quicklogic/add_sub.ys
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@ -3,9 +3,9 @@ hierarchy -top top
equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 3 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 4 t:LUT4
select -assert-count 2 t:LUT2
select -assert-count 8 t:LUT3
select -assert-count 2 t:LUT4
select -assert-count 8 t:inpad
select -assert-count 8 t:outpad
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D