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quicklogic: ABC9 synthesis

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Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
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6
tests/arch/quicklogic/add_sub.ys
View file

@ -3,9 +3,9 @@ hierarchy -top top
equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 3 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 4 t:LUT4
select -assert-count 2 t:LUT2
select -assert-count 8 t:LUT3
select -assert-count 2 t:LUT4
select -assert-count 8 t:inpad
select -assert-count 8 t:outpad
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D

6
tests/arch/quicklogic/counter.ys
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@ -6,9 +6,9 @@ equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogi
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 5 t:LUT2
select -assert-count 2 t:LUT3
select -assert-count 3 t:LUT4
select -assert-count 3 t:LUT2
select -assert-count 5 t:LUT3
select -assert-count 1 t:LUT4
select -assert-count 8 t:dffepc
select -assert-count 1 t:logic_0
select -assert-count 1 t:logic_1

9
tests/arch/quicklogic/fsm.ys
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@ -11,14 +11,13 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 3 t:LUT2
select -assert-count 6 t:LUT3
select -assert-count 7 t:LUT4
select -assert-count 6 t:dffepc
select -assert-count 1 t:LUT2
select -assert-count 9 t:LUT3
select -assert-count 4 t:dffepc
select -assert-count 1 t:logic_0
select -assert-count 1 t:logic_1
select -assert-count 3 t:inpad
select -assert-count 2 t:outpad
select -assert-count 1 t:ckpad
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D

5
tests/arch/quicklogic/latches.ys
View file

@ -32,8 +32,9 @@ proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT3
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4
select -assert-count 5 t:inpad
select -assert-count 1 t:outpad
select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D

4
tests/arch/quicklogic/logic.ys
View file

@ -7,8 +7,8 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
select -assert-count 2 t:LUT3
select -assert-count 8 t:inpad
select -assert-count 10 t:outpad
select -assert-none t:LUT1 t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D

4
tests/arch/quicklogic/mux.ys
View file

@ -30,13 +30,13 @@ proc
equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 4 t:LUT2
select -assert-count 1 t:LUT1
select -assert-count 1 t:LUT3
select -assert-count 2 t:mux4x0
select -assert-count 11 t:inpad
select -assert-count 1 t:outpad
select -assert-none t:LUT2 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
design -load read
hierarchy -top mux16