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quicklogic: ABC9 synthesis

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Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
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5
techlibs/quicklogic/pp3_cells_sim.v
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@ -147,11 +147,10 @@ module dffepc (
);
parameter [0:0] INIT = 1'b0;
// The CLR => Q and PRE => Q paths are commented out due to YosysHQ/yosys#2530.
specify
if (EN) (posedge CLK => (Q : D)) = 1701; // QCK -> QZ
// if (CLR) (CLR => Q) = 967; // QRT -> QZ
// if (PRE) (PRE => Q) = 1252; // QST -> QZ
if (CLR) (CLR => Q) = 967; // QRT -> QZ
if (PRE) (PRE => Q) = 1252; // QST -> QZ
$setup(D, posedge CLK, 216); // QCK -> QDS
$setup(EN, posedge CLK, 590); // QCK -> QEN
endspecify