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quicklogic: ABC9 synthesis

This commit is contained in:
Lofty 2021-04-12 10:33:40 +01:00 committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions

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@ -0,0 +1,14 @@
module $__PP3_DFFEPC_SYNCONLY (
output Q,
input D,
input CLK,
input EN,
);
// For some reason ABC9 adds init attributes to wires even though they were removed before mapping.
// As a workaround, remove any init attributes that get reintroduced.
wire _TECHMAP_REMOVEINIT_Q_ = 1;
dffepc _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1'b0), .CLR(1'b0));
endmodule