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quicklogic: ABC9 synthesis

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Lofty 2021-04-12 10:33:40 +01:00 • committed by Marcelina Kościelnicka
parent a58571d0fe
commit dce037a62c
12 changed files with 97 additions and 22 deletions
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4
techlibs/quicklogic/Makefile.inc
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@ -7,3 +7,7 @@ $(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v))
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v))
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v))
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v))
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v))
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v))