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Updated simlib to new $mem/$memwr interface

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This commit is contained in:
Clifford Wolf 2014-07-16 11:46:40 +02:00
parent 73e0e13d2f
commit dcdd5c11b4
1 changed files with 55 additions and 30 deletions
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85
techlibs/common/simlib.v
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@ -1264,7 +1264,8 @@ parameter WIDTH = 8;
parameter CLK_ENABLE = 0; parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0; parameter CLK_POLARITY = 0;
input CLK, EN; input CLK;
input [WIDTH-1:0] EN;
input [ABITS-1:0] ADDR; input [ABITS-1:0] ADDR;
input [WIDTH-1:0] DATA; input [WIDTH-1:0] DATA;
@ -1300,7 +1301,8 @@ input [RD_PORTS-1:0] RD_CLK;
input [RD_PORTS*ABITS-1:0] RD_ADDR; input [RD_PORTS*ABITS-1:0] RD_ADDR;
output reg [RD_PORTS*WIDTH-1:0] RD_DATA; output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
input [WR_PORTS-1:0] WR_CLK, WR_EN; input [WR_PORTS-1:0] WR_CLK;
input [WR_PORTS*WIDTH-1:0] WR_EN;
input [WR_PORTS*ABITS-1:0] WR_ADDR; input [WR_PORTS*ABITS-1:0] WR_ADDR;
input [WR_PORTS*WIDTH-1:0] WR_DATA; input [WR_PORTS*WIDTH-1:0] WR_DATA;
@ -1338,46 +1340,69 @@ generate
end end
for (i = 0; i < WR_PORTS; i = i+1) begin:wr for (i = 0; i < WR_PORTS; i = i+1) begin:wr
integer k; integer k, n;
reg found_collision; reg found_collision, run_update;
if (WR_CLK_ENABLE[i] == 0) begin:wr_noclk if (WR_CLK_ENABLE[i] == 0) begin:wr_noclk
always @(WR_ADDR or WR_DATA or WR_EN) begin always @(WR_ADDR or WR_DATA or WR_EN) begin
if (WR_EN[i]) begin run_update = 0;
found_collision = 0; for (n = 0; n < WIDTH; n = n+1) begin
for (k = i+1; k < WR_PORTS; k = k+1) if (WR_EN[i][n]) begin
if (WR_EN[k] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ]) found_collision = 0;
found_collision = 1; for (k = i+1; k < WR_PORTS; k = k+1)
if (!found_collision) begin if (WR_EN[k][n] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ])
data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ] <= WR_DATA[ i*WIDTH +: WIDTH ]; found_collision = 1;
update_async_rd <= 1; update_async_rd <= 0; if (!found_collision) begin
data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ][n] <= WR_DATA[ i*WIDTH +: WIDTH ][n];
run_update = 1;
end
end end
end end
if (run_update) begin
update_async_rd <= 1;
update_async_rd <= 0;
end
end end
end else end else
if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
always @(posedge WR_CLK[i]) always @(posedge WR_CLK[i]) begin
if (WR_EN[i]) begin run_update = 0;
found_collision = 0; for (n = 0; n < WIDTH; n = n+1) begin
for (k = i+1; k < WR_PORTS; k = k+1) if (WR_EN[i][n]) begin
if (WR_EN[k] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ]) found_collision = 0;
found_collision = 1; for (k = i+1; k < WR_PORTS; k = k+1)
if (!found_collision) begin if (WR_EN[k][n] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ])
data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ] <= WR_DATA[ i*WIDTH +: WIDTH ]; found_collision = 1;
update_async_rd <= 1; update_async_rd <= 0; if (!found_collision) begin
data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ][n] <= WR_DATA[ i*WIDTH +: WIDTH ][n];
run_update = 1;
end
end end
end end
if (run_update) begin
update_async_rd <= 1;
update_async_rd <= 0;
end
end
end else begin:rd_negclk end else begin:rd_negclk
always @(negedge WR_CLK[i]) always @(negedge WR_CLK[i]) begin
if (WR_EN[i]) begin run_update = 0;
found_collision = 0; for (n = 0; n < WIDTH; n = n+1) begin
for (k = i+1; k < WR_PORTS; k = k+1) if (WR_EN[i][n]) begin
if (WR_EN[k] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ]) found_collision = 0;
found_collision = 1; for (k = i+1; k < WR_PORTS; k = k+1)
if (!found_collision) begin if (WR_EN[k][n] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ])
data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ] <= WR_DATA[ i*WIDTH +: WIDTH ]; found_collision = 1;
update_async_rd <= 1; update_async_rd <= 0; if (!found_collision) begin
data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ][n] <= WR_DATA[ i*WIDTH +: WIDTH ][n];
run_update = 1;
end
end end
end end
if (run_update) begin
update_async_rd <= 1;
update_async_rd <= 0;
end
end
end end
end end