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Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566)
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TimRudy
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3 changed files with 445 additions and 2 deletions
213
tests/verilog/delay_mintypmax.ys
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213
tests/verilog/delay_mintypmax.ys
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@ -0,0 +1,213 @@
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logger -expect-no-warnings
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read_verilog <<EOT
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module test (a, b, c, y);
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input a;
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input signed [1:0] b;
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input signed [2:0] c;
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output y;
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assign #(12.5 : 14.5 : 20) y = ^(a ? b : c);
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog << EOT
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module test (input [7:0] a, b, c, d, output [7:0] x, y, z);
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assign #(20:20:25) x = a + b, y = b + c, z = c + d;
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog << EOT
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module test (input [7:0] a, b, c, d, output [7:0] x, y, z);
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assign #(20:20:25, 40:45:50, 60:65:75) x = a + b, y = b + c, z = c + d;
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test (a, b, c, y);
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localparam TIME_STEP = 0.011;
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input signed [3:0] a;
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input signed [1:0] b;
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input signed [1:0] c;
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output [5:0] y;
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assign #(TIME_STEP:TIME_STEP:TIME_STEP) y = (a >> b) >>> c;
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test;
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wire o, a, b;
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and #(1:2:3, 4:5:6) and_gate (o, a, b);
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wire #(1:2:3, 4:5:6, 7:8:9) x;
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assign o = x;
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test;
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localparam TIME_TYP = 0.7;
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wire o, a, b;
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and #(0:TIME_TYP:2) and_gate (o, a, b);
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wire #(2:TIME_TYP:4) x;
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assign o = x;
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endmodule
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EOT
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design -reset
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logger -expect warning "Yosys has only limited support for tri-state logic at the moment." 1
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read_verilog <<EOT
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module test (input en, input a, input b, output c);
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wire [15:0] add0_res = a + b;
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assign #(15:20:30) c = (en) ? a : 1'bz;
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test (input en, d, t_min, t, t_max);
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reg o;
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always @*
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if (en)
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o = #(t_min : t : t_max, t_min : t : t_max) ~d;
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test #(parameter DELAY_RISE = 0, DELAY_FALL = 0, DELAY_Z = 0)
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(input clock, input reset, input req_0, input req_1, output gnt_0, output gnt_1);
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parameter SIZE = 3;
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parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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reg gnt_0, gnt_1;
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always @ (state or req_0 or req_1)
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begin : FSM_COMBO
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next_state = 3'b000;
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case (state)
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IDLE : if (req_0 == 1'b1) begin
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next_state = #(DELAY_RISE-1 : DELAY_RISE : DELAY_RISE+1) GNT0;
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end else if (req_1 == 1'b1) begin
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next_state = #(DELAY_FALL/1.2 : DELAY_FALL : DELAY_FALL*2.5) GNT1;
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end else begin
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next_state = #(DELAY_Z : DELAY_Z : DELAY_Z) IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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#(DELAY_RISE : DELAY_RISE : DELAY_FALL) next_state = GNT0;
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end else begin
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#DELAY_RISE next_state = IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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#10 next_state = GNT1;
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end else begin
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#(10:10:15, 20:25:25) next_state = IDLE;
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end
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default : next_state = IDLE;
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endcase
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end
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always @ (posedge clock)
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begin : FSM_SEQ
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if (reset == 1'b1) begin
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#(10:10:15) state <= IDLE;
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end else begin
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#(10) state <= next_state;
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end
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end
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always @ (posedge clock)
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begin : FSM_OUTPUT
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if (reset == 1'b1) begin
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gnt_0 <= #(8:9:10) 1'b0;
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gnt_1 <= #1 1'b0;
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end else begin
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case (state)
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IDLE : begin
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gnt_0 <= #(8:9:10) 1'b0;
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gnt_1 <= #1 1'b0;
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end
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GNT0 : begin
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gnt_0 <= #(4:5:6,8:9:10) 1'b1;
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gnt_1 <= #1 1'b0;
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end
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GNT1 : begin
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gnt_0 <= #(2:3:4,4:5:6,8:9:10) 1'b0;
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gnt_1 <= #1 1'b1;
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end
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default : begin
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gnt_0 <= 1'b0;
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gnt_1 <= 1'b0;
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end
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endcase
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end
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end
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test;
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reg q;
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initial begin
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q = 1;
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#(1:2:2) q = 0;
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end
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test #(parameter hyst = 16)
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(input [0:1] inA, input rst, output reg out);
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parameter real updatePeriod = 100.0;
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initial out = 1'b0;
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always #(updatePeriod-5:updatePeriod:updatePeriod+5) begin
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if (rst) out <= 1'b0;
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else if (inA[0] > inA[1]) out <= 1'b1;
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else if (inA[0] < inA[1] - hyst) out <= 1'b0;
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end
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test;
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reg clk;
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initial clk = 1'b0;
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always #(100:180:230) clk = ~clk;
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endmodule
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EOT
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design -reset
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logger -expect-no-warnings
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read_verilog <<EOT
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module test;
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reg clk;
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initial clk = 1'b0;
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always clk = #(100:180:230, 100:180:230) ~clk;
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task t_test;
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sig_036_A <= #(2, 4, 5.5) 0;
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sig_036_B <= #(1.3, 3) 0;
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sig_036_S <= #(2) 0;
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#(100 : 200 : 300, 400 : 500 : 600, 700 : 800 : 900);
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sig_036_A <= #(1.5:2.5:3.0, 3:4:5, 7) ~0;
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sig_036_B <= #(2, 4:6:6) ~0;
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sig_036_S <= #(1.5:2.5:3.0) ~0;
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#100;
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endtask
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endmodule
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EOT
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