mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-25 03:16:22 +00:00
Code Activity

check: check bufnorm too

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-05-22 13:11:24 +02:00
parent 4bff2e6340
commit dcc68e49fb
1 changed files with 33 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

54
passes/cmds/check.cc
View file

@ -27,30 +27,37 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
int check_signorm_cell(RTLIL::Module *module, RTLIL::Cell *cell) int check_bufnorm_cell(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
bool bufnorm = module->design->flagBufferedNormalized;
bool signorm = module->design->flagSigNormalized;
if (!bufnorm && !signorm)
return 0;
int counter = 0; int counter = 0;
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
if (cell->port_dir(conn.first) == RTLIL::PD_INPUT) { if (cell->port_dir(conn.first) == RTLIL::PD_INPUT) {
int i = 0; if (signorm) {
for (auto bit : conn.second) { int i = 0;
if (bit.is_wire() && !module->fanout(bit).count(RTLIL::PortBit(cell, conn.first, i))) for (auto bit : conn.second) {
log_warning("sigNorm: fanout index missing entry for cell %s.%s port %s bit %d\n", if (bit.is_wire() && !module->fanout(bit).count(RTLIL::PortBit(cell, conn.first, i)))
log_id(module), log_id(cell), log_id(conn.first), i), counter++; log_warning("sigNorm: fanout index missing entry for cell %s.%s port %s bit %d\n",
++i; log_id(module), log_id(cell), log_id(conn.first), i), counter++;
++i;
}
} }
} else if (!conn.second.empty()) { } else if (!conn.second.empty()) {
if (!conn.second.is_wire()) { if (!conn.second.is_wire()) {
log_warning("sigNorm: cell %s.%s port %s output is not a full wire: %s\n", log_warning("bufNorm: cell %s.%s port %s output is not a full wire: %s\n",
log_id(module), log_id(cell), log_id(conn.first), log_signal(conn.second)); log_id(module), log_id(cell), log_id(conn.first), log_signal(conn.second));
counter++; counter++;
} else { } else {
Wire *w = conn.second.as_wire(); Wire *w = conn.second.as_wire();
if (!w->known_driver()) if (!w->known_driver())
log_warning("sigNorm: cell %s.%s port %s drives wire %s but wire has no driverCell_ set\n", log_warning("bufNorm: cell %s.%s port %s drives wire %s but wire has no driverCell_ set\n",
log_id(module), log_id(cell), log_id(conn.first), log_id(w)), counter++; log_id(module), log_id(cell), log_id(conn.first), log_id(w)), counter++;
else if (w->driverCell() != cell || w->driverPort() != conn.first) else if (w->driverCell() != cell || w->driverPort() != conn.first)
log_warning("sigNorm: wire %s.%s driverCell_/driverPort_ mismatch: recorded driver is cell %s port %s, but cell %s port %s also drives it\n", log_warning("bufNorm: wire %s.%s driverCell_/driverPort_ mismatch: recorded driver is cell %s port %s, but cell %s port %s also drives it\n",
log_id(module), log_id(w), log_id(module), log_id(w),
log_id(w->driverCell()), log_id(w->driverPort()), log_id(w->driverCell()), log_id(w->driverPort()),
log_id(cell), log_id(conn.first)), counter++; log_id(cell), log_id(conn.first)), counter++;
@ -60,27 +67,32 @@ int check_signorm_cell(RTLIL::Module *module, RTLIL::Cell *cell)
return counter; return counter;
} }
int check_signorm_wire(RTLIL::Module *module, RTLIL::Wire *wire) int check_bufnorm_wire(RTLIL::Module *module, RTLIL::Wire *wire)
{ {
bool bufnorm = module->design->flagBufferedNormalized;
bool signorm = module->design->flagSigNormalized;
if (!bufnorm && !signorm)
return 0;
int counter = 0; int counter = 0;
if (wire->known_driver()) { if (wire->known_driver()) {
Cell *driver = wire->driverCell(); Cell *driver = wire->driverCell();
IdString dport = wire->driverPort(); IdString dport = wire->driverPort();
if (!driver->hasPort(dport)) { if (!driver->hasPort(dport)) {
log_warning("sigNorm: wire %s.%s driverPort_ %s does not exist on driverCell_ %s\n", log_warning("bufNorm: wire %s.%s driverPort_ %s does not exist on driverCell_ %s\n",
log_id(module), log_id(wire), log_id(dport), log_id(driver)); log_id(module), log_id(wire), log_id(dport), log_id(driver));
counter++; counter++;
} else { } else {
const SigSpec &dsig = driver->getPort(dport); const SigSpec &dsig = driver->getPort(dport);
if (!dsig.is_wire() || dsig.as_wire() != wire) if (!dsig.is_wire() || dsig.as_wire() != wire)
log_warning("sigNorm: wire %s.%s driverCell_ %s port %s does not connect back to this wire\n", log_warning("bufNorm: wire %s.%s driverCell_ %s port %s does not connect back to this wire\n",
log_id(module), log_id(wire), log_id(driver), log_id(dport)), counter++; log_id(module), log_id(wire), log_id(driver), log_id(dport)), counter++;
if (wire->port_input && !wire->port_output && driver->type != ID($input_port)) if (wire->port_input && !wire->port_output && driver->type != ID($input_port))
log_warning("sigNorm: module input wire %s.%s is driven by non-$input_port cell %s of type %s\n", log_warning("bufNorm: module input wire %s.%s is driven by non-$input_port cell %s of type %s\n",
log_id(module), log_id(wire), log_id(driver), log_id(driver->type)), counter++; log_id(module), log_id(wire), log_id(driver), log_id(driver->type)), counter++;
} }
} else if (wire->port_input && !wire->port_output) { } else if (wire->port_input && !wire->port_output) {
log_warning("sigNorm: module input wire %s.%s has no driverCell_ set\n", log_warning("bufNorm: module input wire %s.%s has no driverCell_ set\n",
log_id(module), log_id(wire)); log_id(module), log_id(wire));
counter++; counter++;
} }
@ -89,6 +101,9 @@ int check_signorm_wire(RTLIL::Module *module, RTLIL::Wire *wire)
int check_signorm_fanout(RTLIL::Module *module) int check_signorm_fanout(RTLIL::Module *module)
{ {
if (!module->design->flagSigNormalized)
return 0;
int counter = 0; int counter = 0;
for (auto &[bit, portbits] : module->signorm_fanout()) { for (auto &[bit, portbits] : module->signorm_fanout()) {
for (auto &pb : portbits) { for (auto &pb : portbits) {
@ -403,8 +418,7 @@ struct CheckPass : public Pass {
coarsened_cells.insert(cell); coarsened_cells.insert(cell);
} }
if (design->flagSigNormalized) counter += check_bufnorm_cell(module, cell);
counter += check_signorm_cell(module, cell);
} }
pool<SigBit> init_bits; pool<SigBit> init_bits;
@ -433,8 +447,7 @@ struct CheckPass : public Pass {
} }
} }
if (design->flagSigNormalized) counter += check_bufnorm_wire(module, wire);
counter += check_signorm_wire(module, wire);
} }
for (auto state : {State::S0, State::S1, State::Sx}) for (auto state : {State::S0, State::S1, State::Sx})
@ -561,8 +574,7 @@ struct CheckPass : public Pass {
} }
} }
if (design->flagSigNormalized) counter += check_signorm_fanout(module);
counter += check_signorm_fanout(module);
} }
log("Found and reported %d problems.\n", counter); log("Found and reported %d problems.\n", counter);