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Add examples/osu035

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Clifford Wolf 2017-05-23 18:38:20 +02:00
parent 664ba4d80e
commit dca3b3cd5f
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examples/osu035/example.ys Normal file
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read_verilog example.v
read_liberty -lib osu035_stdcells.lib
synth -top top
dfflibmap -liberty osu035_stdcells.lib
abc -liberty osu035_stdcells.lib
opt_clean
stat -liberty osu035_stdcells.lib
write_edif example.edif