mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-05 08:30:51 +00:00
Code Activity

Experimental abc_new tests.

Browse source
This commit is contained in:
nella 2026-05-05 10:50:06 +02:00
parent ca88868902
commit dc9109316f
4 changed files with 153 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

14
tests/techmap/abc_new_experimental_sentinel.ys Normal file
View file

@ -0,0 +1,14 @@
read_verilog <<EOT
module top(input a, output y); assign y = a; endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +1/ +1" 3
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect warning "Feature 'abc_new' is experimental" 1
logger -expect warning "Feature 'write_xaiger2' is experimental" 1
logger -expect warning "Feature 'read_xaiger2' is experimental" 1
logger -expect error "Missing mapping \(no 'M' section\)" 1
abc_new -liberty ../../examples/cmos/cmos_cells.lib