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Experimental abc_new tests.

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nella 2026-05-05 10:50:06 +02:00
parent ca88868902
commit dc9109316f
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tests/techmap/abc_new_abc_verify_pass.ys Normal file
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read_verilog <<EOT
module top(input a, input b, output y);
assign y = a & b;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast
logger -expect log "ABC: .*i/o = +2/ +1" 2
logger -expect log "ABC: Warning: The network is combinational\." 1
logger -expect log "ABC: Networks are equivalent\." 1
logger -expect error "Found 1 problems in 'check -assert'" 1
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
check -assert