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Added support for printing the signal map

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AdvaySingh1 2026-03-18 16:23:41 -07:00
parent a3ffc5da30
commit dc73249d8f
2 changed files with 32 additions and 0 deletions
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Makefile
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@ -790,6 +790,7 @@ include $(YOSYS_SRC)/passes/techmap/Makefile.inc
include $(YOSYS_SRC)/backends/verilog/Makefile.inc
include $(YOSYS_SRC)/backends/rtlil/Makefile.inc
include $(YOSYS_SRC)/backends/json/Makefile.inc
include $(YOSYS_SRC)/backends/blif/Makefile.inc
include $(YOSYS_SRC)/techlibs/common/Makefile.inc