mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 09:55:20 +00:00
Code Activity

clockgate: test fine-grained cells

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-09-09 21:03:22 +02:00
parent e64fceef70
commit dc039d8be4
1 changed files with 40 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
tests/techmap/clockgate.ys
View file

@ -36,6 +36,15 @@ module dffe_11( input clk, en,
end end
endmodule endmodule
module dffe_wide_11( input clk, en,
input [3:0] d1, output reg [3:0] q1,
);
always @( posedge clk ) begin
if ( en )
q1 <= d1;
end
endmodule
EOT EOT
proc proc
@ -45,6 +54,8 @@ design -save before
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Test -pos
clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
# falling edge clock flops don't get matched on -pos # falling edge clock flops don't get matched on -pos
@ -58,8 +69,13 @@ select -module dffe_11 -assert-count 1 t:\\pdk_icg
select -module dffe_10 -assert-count 1 t:\$_NOT_ select -module dffe_10 -assert-count 1 t:\$_NOT_
select -module dffe_11 -assert-count 0 t:\$_NOT_ select -module dffe_11 -assert-count 0 t:\$_NOT_
# Extra credit: multi-bit FFs work fine as well
select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Test -neg
design -load before design -load before
clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
@ -76,6 +92,30 @@ select -module dffe_01 -assert-count 0 t:\$_NOT_
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Same as first case, but on fine-grained cells
design -load before
techmap
clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
# falling edge clock flops don't get matched on -pos
select -module dffe_00 -assert-count 0 t:\\pdk_icg
select -module dffe_01 -assert-count 0 t:\\pdk_icg
# falling edge clock flops do get matched on -pos
select -module dffe_10 -assert-count 1 t:\\pdk_icg
select -module dffe_11 -assert-count 1 t:\\pdk_icg
# if necessary, EN is inverted, since the given ICG
# is assumed to have an active-high EN
select -module dffe_10 -assert-count 1 t:\$_NOT_
select -module dffe_11 -assert-count 0 t:\$_NOT_
# Extra credit: multi-bit FFs work fine as well
select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
#------------------------------------------------------------------------------
design -load before design -load before
clockgate -min_net_size 2 -neg pdk_icg ce:clkin:clkout -tie_lo scanen clockgate -min_net_size 2 -neg pdk_icg ce:clkin:clkout -tie_lo scanen