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Allow $size and $bits in verilog mode, actually check test case

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Clifford Wolf 2017-09-29 11:56:43 +02:00
parent 637a02eb5c
commit dbfd8460a9
3 changed files with 3 additions and 1 deletions
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tests/simple/functions01.sv → tests/sat/sizebits.sv
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tests/sat/sizebits.ys Normal file
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@ -0,0 +1,2 @@
read_verilog -sv sizebits.sv
prep; sat -verify -prove-asserts