mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-22 19:17:55 +00:00
Code Activity

Cleanup

Browse source
This commit is contained in:
Miodrag Milanovic 2024-07-24 13:41:12 +02:00
parent 7bf623a0c7
commit dbf1d037e8
4 changed files with 17 additions and 109 deletions
Download patch file Download diff file Expand all files Collapse all files

30
techlibs/nanoxplore/cells_sim_u.v
View file

@ -12,20 +12,21 @@ module NX_GCK_U(SI1, SI2, CMD, SO);
wire SI2_int = inv_in ? ~SI2 : SI2;
wire SO_int;
generate if (std_mode == "BYPASS") begin
assign SO_int = SI1_int;
end
else if (std_mode == "MUX") begin
assign SO_int = CMD ? SI1_int : SI2_int;
end
else if (std_mode == "CKS") begin
assign SO_int = CMD ? SI1_int : 1'b0;
end
else if (std_mode == "CSC") begin
assign SO_int = CMD;
end
else
$error("Unrecognised std_mode");
generate
if (std_mode == "BYPASS") begin
assign SO_int = SI1_int;
end
else if (std_mode == "MUX") begin
assign SO_int = CMD ? SI1_int : SI2_int;
end
else if (std_mode == "CKS") begin
assign SO_int = CMD ? SI1_int : 1'b0;
end
else if (std_mode == "CSC") begin
assign SO_int = CMD;
end
else
$error("Unrecognised std_mode");
endgenerate
assign SO = inv_out ? ~SO_int : SO_int;
endmodule
@ -302,5 +303,4 @@ module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2);
else
$error("Unknown NX_DDFR_U path");
endgenerate
endmodule