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Include x bits in test of lhs dynamic part-select

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This commit is contained in:
Dag Lem 2023-12-07 13:45:56 +01:00
parent a105d2c050
commit dbec704b49
2 changed files with 5 additions and 5 deletions
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2
tests/verilog/dynamic_range_lhs.sh
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@ -15,7 +15,7 @@ run() {
-p "read_verilog dynamic_range_lhs.v" \ -p "read_verilog dynamic_range_lhs.v" \
-p "proc" \ -p "proc" \
-p "equiv_make gold gate equiv" \ -p "equiv_make gold gate equiv" \
-p "equiv_simple" \ -p "equiv_simple -undef" \
-p "equiv_status -assert" -p "equiv_status -assert"
} }

8
tests/verilog/dynamic_range_lhs.v
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@ -5,8 +5,8 @@ module gate(
input wire [1:0] sel1, sel2 input wire [1:0] sel1, sel2
); );
always @* begin always @* begin
out_u = 0; out_u = 'x;
out_s = 0; out_s = 'x;
case (`SPAN) case (`SPAN)
1: begin 1: begin
out_u[sel1*sel2] = data; out_u[sel1*sel2] = data;
@ -43,8 +43,8 @@ task set;
out_s[b] = data; out_s[b] = data;
endtask endtask
always @* begin always @* begin
out_u = 0; out_u = 'x;
out_s = 0; out_s = 'x;
case (sel1*sel2) case (sel1*sel2)
2'b00: set(0, 0); 2'b00: set(0, 0);
2'b01: set(1, 1); 2'b01: set(1, 1);