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Include x bits in test of lhs dynamic part-select

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This commit is contained in:
Dag Lem 2023-12-07 13:45:56 +01:00
parent a105d2c050
commit dbec704b49
2 changed files with 5 additions and 5 deletions
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2
tests/verilog/dynamic_range_lhs.sh
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@ -15,7 +15,7 @@ run() {
-p "read_verilog dynamic_range_lhs.v" \
-p "proc" \
-p "equiv_make gold gate equiv" \
-p "equiv_simple" \
-p "equiv_simple -undef" \
-p "equiv_status -assert"
}