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rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch

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This commit is contained in:
Emil J. Tywoniak 2026-01-01 17:06:38 +01:00
parent 770d74cc9b
commit dbc7e33908
4 changed files with 1283 additions and 1252 deletions
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62
kernel/unstable/patch.cc
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@ -5,40 +5,50 @@
YOSYS_NAMESPACE_BEGIN
/**
* Notes
*
* If we want GC, we need more indices
* namely user count (and users?). This should be optional
*
*
* Notes
*
* If we want GC, we need more indices
* namely user count (and users?). This should be optional
*
*
*/
using namespace RTLIL;
template class CellAdderMixin<Patch>;
Cell* Patch::addCell(IdString name, IdString type) {
auto& cell = cells_.emplace_back(Cell::ConstructToken{});
auto& cell = cells_.emplace_back(Cell::ConstructToken{});
cell.name = std::move(name);
cell.type = type;
return &cell;
return &cell;
}
Wire* Patch::addWire(IdString name, int width) {
(void)name;
(void)width;
log_assert(false);
return nullptr;
}
void Patch::patch() {
for (auto& cell: cells_) {
Cell* new_cell = mod->addCell(cell.name, &cell);
for (auto [port_name, sig] : new_cell->connections()) {
log_assert(yosys_celltypes.cell_known(cell.type));
auto dir = cell.port_dir(port_name);
if (dir == PD_OUTPUT || dir == PD_INOUT) {
for (auto chunk : sig.chunks()) {
log_assert(chunk.is_wire());
auto* wire = chunk.wire;
// Unwire old driver
wire->driverCell_->setPort(wire->driverPort_, SigSpec());
// Maintain bufnorm
wire->driverCell_ = new_cell;
wire->driverPort_ = port_name;
}
}
}
}
for (auto& cell: cells_) {
Cell* new_cell = mod->addCell(cell.name, &cell);
for (auto [port_name, sig] : new_cell->connections()) {
log_assert(yosys_celltypes.cell_known(cell.type));
auto dir = cell.port_dir(port_name);
if (dir == PD_OUTPUT || dir == PD_INOUT) {
for (auto chunk : sig.chunks()) {
log_assert(chunk.is_wire());
auto* wire = chunk.wire;
// Unwire old driver
wire->driverCell_->setPort(wire->driverPort_, SigSpec());
// Maintain bufnorm
wire->driverCell_ = new_cell;
wire->driverPort_ = port_name;
}
}
}
}
}