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docs: moving code examples

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Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.
This commit is contained in:
Krystine Sherwin 2023-11-14 12:55:39 +13:00
parent 3d70867809
commit dbc38d72cf
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119 changed files with 264 additions and 905 deletions
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23
docs/source/code_examples/show/Makefile Normal file
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PROGRAM_PREFIX :=
YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
EXAMPLE = example_00 example_01 example_02 example_03
EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
CMOS = cmos_00 cmos_01
CMOS_DOTS := $(addsuffix .dot,$(CMOS))
all: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
splice.dot: splice.v
$(YOSYS) -p 'proc; opt; show -format dot -prefix splice' splice.v
$(EXAMPLE_DOTS): example.v example.ys
$(YOSYS) example.ys
cmos_00.dot: cmos.v
$(YOSYS) -p 'read_verilog cmos.v; techmap; abc -liberty ../intro/mycells.lib;; show -format dot -prefix cmos_00'
cmos_01.dot: cmos.v
$(YOSYS) -p 'read_verilog cmos.v; techmap; splitnets -ports; abc -liberty ../intro/mycells.lib;; show -lib ../intro/mycells.v -format dot -prefix cmos_01'